P
Per Stenström
Researcher at Chalmers University of Technology
Publications - 251
Citations - 8514
Per Stenström is an academic researcher from Chalmers University of Technology. The author has contributed to research in topics: Cache & Cache coherence. The author has an hindex of 43, co-authored 245 publications receiving 8193 citations. Previous affiliations of Per Stenström include Stanford University & Ericsson.
Papers
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Journal ArticleDOI
The worst-case execution-time problem—overview of methods and survey of tools
Reinhard Wilhelm,Jakob Engblom,Andreas Ermedahl,Niklas Holsti,Stephan Thesing,David Whalley,Guillem Bernat,Christian Ferdinand,Reinhold Heckmann,Tulika Mitra,Frank Mueller,Isabelle Puaut,Peter Puschner,Jan Staschulat,Per Stenström +14 more
TL;DR: Different approaches to the determination of upper bounds on execution times are described and several commercially available tools1 and research prototypes are surveyed.
Proceedings ArticleDOI
Timing anomalies in dynamically scheduled microprocessors
Thomas Lundqvist,Per Stenström +1 more
TL;DR: This work provides necessary conditions when timing anomalies can show up and identifies what architectural features that may cause such anomalies, and proposes some simple code modification techniques to make it impossible for any anomalies to occur.
Journal ArticleDOI
A survey of cache coherence schemes for multiprocessors
TL;DR: Schemes for cache coherence that exhibit various degrees of hardware complexity, ranging from protocols that maintain coherence in hardware, to software policies that prevent the existence of copies of shared, writable data, are surveyed.
Book ChapterDOI
Parallel Computer Architecture
TL;DR: Computer architecture is a truly fascinating field in which improvements in the basic echnology and innovations how to make best use of he underlying technology has yielded a performance growth exceeding a million times over the past 50 years.
Proceedings ArticleDOI
An adaptive cache coherence protocol optimized for migratory sharing
TL;DR: An adaptive protocol is proposed that effectively eliminates most single invalidations and improves the performance by reducing the shared access penalty and the network traffic.