International Technology Roadmap for Semiconductors 2003の要求清浄度について － シリコンウエハ表面と雰囲気環境に要求される清浄度, 分析方法の現状について －

http://user.it.uu.se/~jarst116/slides/week4.pdf

Graph-Based Algorithms for Boolean Function Manipulation

Principles of Asynchronous Circuit Design - A Systems Perspective addresses the need for an introductory text on asynchronous circuit design. Part I is an 8-chapter tutorial which addresses the most important issues for the beginner, including how to think about asynchronous systems. Part II is a 4-chapter introduction to Balsa, a freely-available synthesis system for asynchronous circuits which will enable the reader to get hands-on experience of designing high-level asynchronous systems. Part III offers a number of examples of state-of-the-art asynchronous systems to illustrate what can be built using asynchronous techniques. The examples range from a complete commercial smart card chip to complex microprocessors. The objective in writing this book has been to enable industrial designers with a background in conventional (clocked) design to be able to understand asynchronous design sufficiently to assess what it has to offer and whether it might be advantageous in their next design task.

/pdf/principles-of-asynchronous-circuit-design-a-systems-58fhcojs1t.pdf

Principles of Asynchronous Circuit Design: A Systems Perspective

We consider a fully SAT-based method of unbounded symbolic model checking based on computing Craig interpolants. In benchmark studies using a set of large industrial circuit verification instances, this method is greatly more efficient than BDD-based symbolic model checking, and compares favorably to some recent SAT-based model checking methods on positive instances.

Interpolation and SAT-based model checking

To alleviate the complex communication problems that arise as the number of on-chip components increases, network-on-chip (NoC) architectures have been recently proposed to replace global interconnects. In this paper, we first provide a general description of NoC architectures and applications. Then, we enumerate several related research problems organized under five main categories: Application characterization, communication paradigm, communication infrastructure, analysis, and solution evaluation. Motivation, problem description, proposed approaches, and open issues are discussed for each problem from system, microarchitecture, and circuit perspectives. Finally, we address the interactions among these research problems and put the NoC design process into perspective.

Outstanding Research Problems in NoC Design: System, Microarchitecture, and Circuit Perspectives

Seminal work by Cortadella, Kondratyev, Lavagno, and Sotiriou includes a hand-written proof that a particular handshaking protocol preserves flow equivalence, a notion of equivalence between synchronous latch-based specifications and their desynchronized bundled-data asynchronous implementations. In this work we identify a counterexample to Cortadella et al.'s proof illustrating how their protocol can in fact lead to a violation of flow equivalence. However, two of the less concurrent protocols identified in their paper do preserve flow equivalence. To verify this fact, we formalize flow equivalence in the Coq proof assistant and provide mechanized, machine-checkable proofs of our results.

Formal Verification of Flow Equivalence in Desynchronized Designs

Digital single-flux quantum (SFQ) technology promises to meet the demands of ultra low power and high speed computing needed for future exascale supercomputing platforms. However, clocking SFQ logic circuits remains a challenge due to the presence of a large number of on-chip clock sinks, and hence, decomposing large designs into multiple independent clock domains similar to CMOS, have been proposed. However, such clock domains demand efficient synchronizing First-in-first-out (FIFO) buffers and robust interfaces to safely transfer data from one clock domain to another. In this brief, we propose such a FIFO synchronizer and clock-domain crossing interface for both uni and bi-directional data transfer without any significant degradation of the clock frequency. Our proposal scales to complex gate-level pipelined SFQ logic cores while demonstrating extremely low Bit Error Rate (BER) and is unaffected by noise, given current SFQ lithography feature sizes.

A High Performance and Robust FIFO Synchronizer-Interface for Crossing Clock Domains in SFQ Logic

The ill effects of process, voltage, and temperature variations are significantly reduced by ring-oscillator (OR)-based clocks and bundled-data (BD) designs. Such designs include delay lines that enable the addition of test margin that can either by set uniformly across all manufactured chips or tuned individually per-chip. This study mathematically analyses the resulting yield subject to a limit on shipped product quality providing a practical mechanism of optimising the test margins for these circuits. The model also provides a means of quantifying the benefits from the correlation in the delay line and combinational logic. In particular, using correlation values obtained from Monte Carlo analysis of a sample circuit in a 65 nm process, the model shows that BD and OR-based circuits can have an over 50% yield advantage over their synchronous counterparts.

https://ietresearch.onlinelibrary.wiley.com/doi/pdf/10.1049/iet-cdt.2018.5040

Yield modelling and analysis of bundled data and ring-oscillator based designs

Introduction The single-track protocol, introduced in Chapter 2, was initially proposed by van Berkel and Blink as a communication method for bundled-data pipeline controllers. As an example, Figure 13.1 shows a single-track synchronization channel implemented with a single wire between a sender and a receiver. In this example, the sender sends a synchronization token by driving the channel wire high and the receiver detects the token and resets the channel by resetting the wire low. This is then detected by the sender, which may send a second token by raising the channel wire high again and thus repeating the entire handshaking process. An alternative form of this protocol is also possible in which the sender drives the communication wire low and the receiver drives it high. Unlike other two-phase protocols, the single-track protocol returns the communication wire to its initial state. This enables single-track templates to react to only one type of transition, avoiding the need for the complex PMOS transistor networks that are a source of area and power inefficiencies for templates that use two-phase transition signaling, i.e. a non-return-to-zero protocol. Moreover, compared with four-phase protocols the single-track protocol has fewer wire transitions, only two instead of four, to complete a handshake, leading to improved power consumption per transmitted bit. Finally, because this protocol does not use an acknowledge wire it requires fewer wires than protocols that use distinct request and acknowledge wires.

A Designer's Guide to Asynchronous VLSI: Single-track pipeline templates

Hyper spectral images (HSI) provide rich spectral and spatial information across a series of contiguous spectral bands. However, the accurate processing of the spectral and spatial correlation between the bands requires the use of energy-expensive 3-D Convolutional Neural Networks (CNNs). To address this challenge, we propose the use of Spiking Neural Networks (SNNs) that are generated from iso-architecture CNNs and trained with quantization-aware gradient descent to optimize their weights, membrane leak, and firing thresholds. During both training and inference, the analog pixel values of a HSI are directly applied to the input layer of the SNN without the need to convert to a spike-train. The reduced latency of our training technique combined with high activation sparsity yields significant improvements in computational efficiency. We evaluate our proposal using three HSI datasets on a 3-D and a 3-D/2-D hybrid convolutional architecture. We achieve overall accuracy, average accuracy, and kappa coefficient of 98.68%, 98.34%, and 98.20% respectively with 5 time steps (inference latency) and 6-bit weight quantization on the Indian Pines dataset. In particular, our models achieved accuracies similar to state-of-the-art (SOTA) with 560.6 and 44.8 times less compute energy on average over three HSI datasets than an iso-architecture full-precision and 6-bit quantized CNN, respectively.

Peter A. Beerel

Papers

Formal Verification of Flow Equivalence in Desynchronized Designs

A High Performance and Robust FIFO Synchronizer-Interface for Crossing Clock Domains in SFQ Logic

Yield modelling and analysis of bundled data and ring-oscillator based designs

A Designer's Guide to Asynchronous VLSI: Single-track pipeline templates

HYPER-SNN: Towards Energy-efficient Quantized Deep Spiking Neural Networks for Hyperspectral Image Classification.