P
Peter A. Beerel
Researcher at University of Southern California
Publications - 236
Citations - 3784
Peter A. Beerel is an academic researcher from University of Southern California. The author has contributed to research in topics: Asynchronous communication & Computer science. The author has an hindex of 30, co-authored 208 publications receiving 3403 citations. Previous affiliations of Peter A. Beerel include Intel & University of California, San Diego.
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Proceedings ArticleDOI
Safe BDD minimization using don't cares
TL;DR: Algorithms that minimize the size of BDDs representing incompletelyspecified functions by intelligently assigning don't cares tobinary values are presented, thereby significantly reducing peakmemory requirements.
Proceedings ArticleDOI
The design and verification of a high-performance low-control-overhead asynchronous differential equation solver
TL;DR: This paper describes the design and verification of a high-performance asynchronous differential equation solver that has low control overhead which allows the average-case delay to be 48% faster than any comparable synchronous design.
Proceedings ArticleDOI
Symbolic techniques for performance analysis of timed systems based on average time separation of events
Aiguo Xie,Peter A. Beerel +1 more
TL;DR: This work model the system as a set of probabilistic finite state machines which is analyzed as a discrete time Markov chain and the stationary probability of all reachable states is obtained iteratively using ADDs.
Journal ArticleDOI
ColdFlux Superconducting EDA and TCAD Tools Project: Overview and Progress
Coenrad J. Fourie,Kyle Jackman,Matthys M. Botha,Sasan Razmkhah,Pascal Febvre,Christopher L. Ayala,Qiuyun Xu,Nobuyuki Yoshikawa,Erin Patrick,Mark E. Law,Yanzi Wang,Murali Annavaram,Peter A. Beerel,Sandeep K. S. Gupta,Shaheen Nazarian,Massoud Pedram +15 more
TL;DR: An overview of the current and planned activities related to the ColdFlux project is presented and the design assumptions and decisions that were made to allow the development of design tools for million-gate circuits are justified.
Proceedings ArticleDOI
Blade -- A Timing Violation Resilient Asynchronous Template
Dylan Hand,Matheus T. Moreira,Hsin-Ho Huang,Danlei Chen,Frederico Butzke,Zhichao Li,Matheus Gibiluka,Melvin A. Breuer,Ney Calazans,Peter A. Beerel +9 more
TL;DR: Results demonstrate that a nominal area overhead of the asynchronous template of less than 10% leads to a 19% performance boost over the synchronous design due to average-case data and a 30-40% improvement when synchronous PVT margins are considered.