International Technology Roadmap for Semiconductors 2003の要求清浄度について － シリコンウエハ表面と雰囲気環境に要求される清浄度, 分析方法の現状について －

http://user.it.uu.se/~jarst116/slides/week4.pdf

Graph-Based Algorithms for Boolean Function Manipulation

Principles of Asynchronous Circuit Design - A Systems Perspective addresses the need for an introductory text on asynchronous circuit design. Part I is an 8-chapter tutorial which addresses the most important issues for the beginner, including how to think about asynchronous systems. Part II is a 4-chapter introduction to Balsa, a freely-available synthesis system for asynchronous circuits which will enable the reader to get hands-on experience of designing high-level asynchronous systems. Part III offers a number of examples of state-of-the-art asynchronous systems to illustrate what can be built using asynchronous techniques. The examples range from a complete commercial smart card chip to complex microprocessors. The objective in writing this book has been to enable industrial designers with a background in conventional (clocked) design to be able to understand asynchronous design sufficiently to assess what it has to offer and whether it might be advantageous in their next design task.

/pdf/principles-of-asynchronous-circuit-design-a-systems-58fhcojs1t.pdf

Principles of Asynchronous Circuit Design: A Systems Perspective

We consider a fully SAT-based method of unbounded symbolic model checking based on computing Craig interpolants. In benchmark studies using a set of large industrial circuit verification instances, this method is greatly more efficient than BDD-based symbolic model checking, and compares favorably to some recent SAT-based model checking methods on positive instances.

Interpolation and SAT-based model checking

To alleviate the complex communication problems that arise as the number of on-chip components increases, network-on-chip (NoC) architectures have been recently proposed to replace global interconnects. In this paper, we first provide a general description of NoC architectures and applications. Then, we enumerate several related research problems organized under five main categories: Application characterization, communication paradigm, communication infrastructure, analysis, and solution evaluation. Motivation, problem description, proposed approaches, and open issues are discussed for each problem from system, microarchitecture, and circuit perspectives. Finally, we address the interactions among these research problems and put the NoC design process into perspective.

Outstanding Research Problems in NoC Design: System, Microarchitecture, and Circuit Perspectives

This paper surveys the most promising low-power and energy-efficient asynchronous design techniques that can lead to substantial advantages over synchronous counterparts. Our discussions cover macro-architectural, micro-architectural, and circuit-level differences between asynchronous and synchronous implementations in a wide range of designs, applications, and domains including microprocessors, application specific designs, and networks on chip.

Low Power and Energy Efficient Asynchronous Design

This paper presents an efficient method for state classification of finite state Markov chains using BDD-based symbolic techniques. The method exploits the fundamental properties of a Markov chain and classifies the state space by iteratively applying reachability analysis. We compare our method with the current state-of-the-art technique which requires the computation of the transitive closure of the transition relation of a Markov chain. Experiments in over a dozen synchronous and asynchronous systems demonstrate that our method dramatically reduces the CPU time needed, and solves much larger problems because of reduced memory requiremen ts.

Efficient state classification of finite state Markov chains

This paper presents a dynamic network rewiring (DNR) method to generate pruned deep neural network (DNN) models that are robust against adversarial attacks yet maintain high accuracy on clean images. In particular, the disclosed DNR method is based on a unified constrained optimization formulation using a hybrid loss function that merges ultra-high model compression with robust adversarial training. This training strategy dynamically adjusts inter-layer connectivity based on per-layer normalized momentum computed from the hybrid loss function. In contrast to existing robust pruning frameworks that require multiple training iterations, the proposed learning strategy achieves an overall target pruning ratio with only a single training iteration and can be tuned to support both irregular and structured channel pruning. To evaluate the merits of DNR, experiments were performed with two widely accepted models, namely VGG16 and ResNet-18, on CIFAR-10, CIFAR-100 as well as with VGG16 on Tiny-ImageNet. Compared to the baseline uncompressed models, DNR provides over20x compression on all the datasets with no significant drop in either clean or adversarial classification accuracy. Moreover, our experiments show that DNR consistently finds compressed models with better clean and adversarial image classification performance than what is achievable through state-of-the-art alternatives.

A Tunable Robust Pruning Framework Through Dynamic Network Rewiring of DNNs.

In this paper, we propose a novel low swing driver using a Dynamic Diode-Connected Driver (DDCD) architecture. The receiver can be a simple inverter since the line swing is around Vdd/2 (from Vtn to Vdd- |Vtp|). The simulation results shows a reduction of the energy-delay product between 27% and 54% when compared with the full swing CMOS buffer for a 0.5µm and 0.18 µm process. Unlike most alternatives, no extra power supplies, nor a multi-threshold process, are required.

/pdf/low-swing-signaling-using-a-dynamic-diode-connected-driver-16pvfcw1l9.pdf

Low swing signaling using a dynamic diode-connected driver

This paper presents technology mapping techniques that optimize for average case delay of asynchronous burst-mode control circuits. First, the specification of the circuit is analyzed using stochastic techniques to determine the relative frequency of occurrence of each state transition. Then, subject to timing and area constraints, the technology mapper minimizes the sum of the cycle times of the state transitions, weighted by their relative frequencies. Unlike other technology mappers, our mapper is based on the single step transition model for delay which finds the true critical paths, avoiding the false path problem.

Peter A. Beerel

Papers

Low Power and Energy Efficient Asynchronous Design

Efficient state classification of finite state Markov chains

A Tunable Robust Pruning Framework Through Dynamic Network Rewiring of DNNs.

Low swing signaling using a dynamic diode-connected driver

Optimizing average-case delay in technology mapping of burst-mode circuits