International Technology Roadmap for Semiconductors 2003の要求清浄度について － シリコンウエハ表面と雰囲気環境に要求される清浄度, 分析方法の現状について －

http://user.it.uu.se/~jarst116/slides/week4.pdf

Graph-Based Algorithms for Boolean Function Manipulation

Principles of Asynchronous Circuit Design - A Systems Perspective addresses the need for an introductory text on asynchronous circuit design. Part I is an 8-chapter tutorial which addresses the most important issues for the beginner, including how to think about asynchronous systems. Part II is a 4-chapter introduction to Balsa, a freely-available synthesis system for asynchronous circuits which will enable the reader to get hands-on experience of designing high-level asynchronous systems. Part III offers a number of examples of state-of-the-art asynchronous systems to illustrate what can be built using asynchronous techniques. The examples range from a complete commercial smart card chip to complex microprocessors. The objective in writing this book has been to enable industrial designers with a background in conventional (clocked) design to be able to understand asynchronous design sufficiently to assess what it has to offer and whether it might be advantageous in their next design task.

/pdf/principles-of-asynchronous-circuit-design-a-systems-58fhcojs1t.pdf

Principles of Asynchronous Circuit Design: A Systems Perspective

We consider a fully SAT-based method of unbounded symbolic model checking based on computing Craig interpolants. In benchmark studies using a set of large industrial circuit verification instances, this method is greatly more efficient than BDD-based symbolic model checking, and compares favorably to some recent SAT-based model checking methods on positive instances.

Interpolation and SAT-based model checking

To alleviate the complex communication problems that arise as the number of on-chip components increases, network-on-chip (NoC) architectures have been recently proposed to replace global interconnects. In this paper, we first provide a general description of NoC architectures and applications. Then, we enumerate several related research problems organized under five main categories: Application characterization, communication paradigm, communication infrastructure, analysis, and solution evaluation. Motivation, problem description, proposed approaches, and open issues are discussed for each problem from system, microarchitecture, and circuit perspectives. Finally, we address the interactions among these research problems and put the NoC design process into perspective.

Outstanding Research Problems in NoC Design: System, Microarchitecture, and Circuit Perspectives

This paper presents the design of a channel-based asynchronous sequential decoder implemented with quasi-delay-insensitive templates. The Powermill simulation results in TSMC 0.25-CMOS technology show that the circuit runs at 430 MHz and consumes 32 mW. Techniques to effectively partition and implement the top level design, the implementation of fast shift registers, memories, and various other structures are discussed. Compared to a previously designed synchronous Fano decoder, the asynchronous version consumes 1/3 the power and runs at 2.15 times the speed assuming standard process normalization. The design also highlights the introduction of a standard-cell library and back-end design flow for asynchronous designs based on precharged half buffer (PCHB) templates

An Asynchronous Low-Power High-Performance Sequential Decoder Implemented With QDI Templates

This paper presents a technology mapping technique for optimizing the average-case delay of asynchronous combinational circuits implemented using domino logic and one-hot encoded outputs. The technique minimizes the critical path for common input patterns at the possible expense of making less common critical paths longer. To demonstrate the application of this technique, we present a case study of a combinational length decoding block, an integral component of an Asynchronous Instruction Length Decoder (AILD) which can be used in Pentium(R) processors. The experimental results demonstrate that the average-case delay of our mapped circuits can be dramatically lower than the worst-case delay of the circuits obtained using conventional worst-case mapping techniques.

Average-case optimized technology mapping of one-hot domino circuits

This paper addresses the problem of identifying the minimal pipelining needed in an asynchronous circuit (e.g., number/size of pipeline stages/latches required) to satisfy a given performance constraint, thereby implicitly minimizing area and power for a given performance. In contrast to the somewhat analogous problem of retiming in the synchronous domain, we first show that the basic pipeline optimization problem for asynchronous circuits is NP-complete. This paper then presents an efficient branch and bound algorithm that can find the optimal pipeline configuration for moderately-sized problems. Our experimental results on a few scalable system models demonstrate that our novel branch and bound solver can find the optimal pipeline configuration for models that have up to 2/sup 35/ possible pipeline configurations.

Pipeline optimization for asynchronous circuits: complexity analysis and an efficient optimal algorithm

Neural networks have proven to be extremely powerful tools for modern artificial intelligence applications, but computational and storage complexity remain limiting factors. This paper presents two compatible contributions towards reducing the time, energy, computational, and storage complexities associated with multilayer perceptrons. Pre-defined sparsity is proposed to reduce the complexity during both training and inference, regardless of the implementation platform. Our results show that storage and computational complexity can be reduced by factors greater than 5X without significant performance loss. The second contribution is an architecture for hardware acceleration that is compatible with pre-defined sparsity. This architecture supports both training and inference modes and is flexible in the sense that it is not tied to a specific number of neurons. For example, this flexibility implies that various sized neural networks can be supported on various sized field programmable gate array (FPGA)s.

Pre-Defined Sparse Neural Networks With Hardware Acceleration

Techniques are described for converting netlists for synchronous circuits such as combinational modules, flip flops (or latches), and clock gating modules, to netlist of asynchronous modules. Processes including algorithms are described that bundle multiple modules in an enable domain, so that they are activated only if the incoming enable token to the enable domain has the UPDATE value. The modules can be clustered inside an enable domain, so that each cluster has a separate controller. The objective function of bundling and clustering can minimize power consumption with respect to a given cycle time. Exemplary embodiments can include a gated multilevel domino template.

Peter A. Beerel

Papers

An Asynchronous Low-Power High-Performance Sequential Decoder Implemented With QDI Templates

Average-case optimized technology mapping of one-hot domino circuits

Pipeline optimization for asynchronous circuits: complexity analysis and an efficient optimal algorithm

Pre-Defined Sparse Neural Networks With Hardware Acceleration

Power aware asynchronous circuits