International Technology Roadmap for Semiconductors 2003の要求清浄度について － シリコンウエハ表面と雰囲気環境に要求される清浄度, 分析方法の現状について －

http://user.it.uu.se/~jarst116/slides/week4.pdf

Graph-Based Algorithms for Boolean Function Manipulation

Principles of Asynchronous Circuit Design - A Systems Perspective addresses the need for an introductory text on asynchronous circuit design. Part I is an 8-chapter tutorial which addresses the most important issues for the beginner, including how to think about asynchronous systems. Part II is a 4-chapter introduction to Balsa, a freely-available synthesis system for asynchronous circuits which will enable the reader to get hands-on experience of designing high-level asynchronous systems. Part III offers a number of examples of state-of-the-art asynchronous systems to illustrate what can be built using asynchronous techniques. The examples range from a complete commercial smart card chip to complex microprocessors. The objective in writing this book has been to enable industrial designers with a background in conventional (clocked) design to be able to understand asynchronous design sufficiently to assess what it has to offer and whether it might be advantageous in their next design task.

/pdf/principles-of-asynchronous-circuit-design-a-systems-58fhcojs1t.pdf

Principles of Asynchronous Circuit Design: A Systems Perspective

We consider a fully SAT-based method of unbounded symbolic model checking based on computing Craig interpolants. In benchmark studies using a set of large industrial circuit verification instances, this method is greatly more efficient than BDD-based symbolic model checking, and compares favorably to some recent SAT-based model checking methods on positive instances.

Interpolation and SAT-based model checking

To alleviate the complex communication problems that arise as the number of on-chip components increases, network-on-chip (NoC) architectures have been recently proposed to replace global interconnects. In this paper, we first provide a general description of NoC architectures and applications. Then, we enumerate several related research problems organized under five main categories: Application characterization, communication paradigm, communication infrastructure, analysis, and solution evaluation. Motivation, problem description, proposed approaches, and open issues are discussed for each problem from system, microarchitecture, and circuit perspectives. Finally, we address the interactions among these research problems and put the NoC design process into perspective.

Outstanding Research Problems in NoC Design: System, Microarchitecture, and Circuit Perspectives

This paper presents an efficient method for state classification of finite-state Markov chains using binary-decision diagram-based symbolic techniques. The method exploits the fundamental properties of a Markov chain and classifies the state space by iteratively applying reachability analysis. We compare our method with the state-of-the-art technique, which requires the transitive closure of the transition relation of a Markov chain. Experiments in over a dozen synchronous and asynchronous systems and queueing networks demonstrate that our method dramatically reduces the CPU time needed and solves much larger problems because of the reduced memory requirements.

Efficient state classification of finite-state Markov chains

An instruction execution pipeline in a computer system having variable-length instructions uses branch prediction to perform self-timed marking of instructions prior to decoding. Branch handling logic is provided in an instruction marking circuit to directly mark a target instruction of a predicted branch as the next instruction to be decoded. Additionally, a branch target FIFO may be used to store information about the location of the target instruction in the instruction stream.

Branch instruction handling in a self-timed marking system

This chapter describes and extends a recently developed approach for analyzing the performance of asynchronous circuits using stochastic timed Petri nets (STPNs) with unique- and free-choice and general delay distributions. The approach uses finite net executions to derive closed-form expressions for both upper and lower bounds of the performance metrics. The expressions can be efficiently evaluated using standard statistical methods. The mean of the upper and lower bounds provides an performance estimate which has a well-defined error interval. The error interval can often be made arbitrarily small by analyzing longer net executions at the cost of additional run-time. Experiments of several asynchronous circuits demonstrate the efficiency of the approach as well as the high quality of the estimates. The experiments include a fullscale STPN model of Intel’s asynchronous instruction length decoding and steering unit with over 900 transitions and 500 places.

Performance Analysis of Asynchronous Circuits and Systems Using Stochastic Timed Petri Nets

Although many applications could benefit from the advantages of asynchronous circuits, the time-to-market pressures faced by industry designers force the use of synchronous design styles for which numerous mature computer-aided-design (CAD) tools are available. Recently, however, heightened interest in low power consumption and growing concern over clock skew has encouraged the use of asynchronous techniques as a viable approach to future circuit design. This thesis details our developments in the synthesis, verification, and testability of speed-independent circuits, a class of asynchronous circuits guaranteed to function correctly regardless of individual gate delays. We use a state graph as a specification language because of its compatibility with a variety of high-level languages, allowing the designer to choose between several specification formats. We developed a synthesis tool that generates correct gate-level speed-independent circuits suitable for standard-cell and gate-array implementations. The synthesized circuits are on average approximately 25% faster and 5% smaller when compared to circuits in which delay elements are added to avoid circuit hazards. Although most synthesis methods ensure correct circuits by construction, verification has proven to be a necessary part of the design cycle because it provides a means of debugging synthesis tools and checking hand optimizations. We have developed a verification tool that implements an efficient conservative verification algorithm which has exponentially lower complexity than traditional tools. Experimental results on a large benchmark of circuits taken from industry and academia demonstrate that, in practice, our tool yields no false negatives, verifies large circuits that can not be verified using traditional tools, and verifies small circuits up to two or three orders of magnitude faster than traditional tools. In addition, we addressed the testability property of such circuits, including discovering a self-checking property of speed-independent circuits for multiple output stuck-at-faults. This thesis describes an integrated approach to the computer-aided design of speed-independent circuits, making asynchronous circuits a feasible alternative to more traditional synchronous circuits.

CAD tools for the synthesis, verification, and testability of robust asynchronous circuits

This paper presents theory and algorithms for the synthesis of standard C-implementations of speed-independent circuits. These implementations are block-level circuits which may consist of atomic gates to perform complex functions in order to ensure hazard freedom. First, we present Boolean covering conditions that guarantee that the standard C-implementations operate correctly. Then, we present two algorithms that produce optimal solutions to the covering problem. The first algorithm is always applicable, but does not complete on large circuits. The second algorithm, motivated by our observation that our covering problem can often be solved with a single cube, finds the optimal single-cube solution when such a solution exists. When applicable, the second algorithm is dramatically more efficient than the first, more general algorithm. We present results for benchmark specifications which indicate that our single-cube algorithm is applicable on most benchmark circuits and reduces run times by over an order of magnitude. The block-level circuits generated by our algorithms are a good starting point for tools that perform technology mapping to obtain gate-level speed-independent circuits.

Peter A. Beerel

Papers

Efficient state classification of finite-state Markov chains

Branch instruction handling in a self-timed marking system

Performance Analysis of Asynchronous Circuits and Systems Using Stochastic Timed Petri Nets

CAD tools for the synthesis, verification, and testability of robust asynchronous circuits

Covering conditions and algorithms for the synthesis of speed-independent circuits