International Technology Roadmap for Semiconductors 2003の要求清浄度について － シリコンウエハ表面と雰囲気環境に要求される清浄度, 分析方法の現状について －

http://user.it.uu.se/~jarst116/slides/week4.pdf

Graph-Based Algorithms for Boolean Function Manipulation

Principles of Asynchronous Circuit Design - A Systems Perspective addresses the need for an introductory text on asynchronous circuit design. Part I is an 8-chapter tutorial which addresses the most important issues for the beginner, including how to think about asynchronous systems. Part II is a 4-chapter introduction to Balsa, a freely-available synthesis system for asynchronous circuits which will enable the reader to get hands-on experience of designing high-level asynchronous systems. Part III offers a number of examples of state-of-the-art asynchronous systems to illustrate what can be built using asynchronous techniques. The examples range from a complete commercial smart card chip to complex microprocessors. The objective in writing this book has been to enable industrial designers with a background in conventional (clocked) design to be able to understand asynchronous design sufficiently to assess what it has to offer and whether it might be advantageous in their next design task.

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Principles of Asynchronous Circuit Design: A Systems Perspective

We consider a fully SAT-based method of unbounded symbolic model checking based on computing Craig interpolants. In benchmark studies using a set of large industrial circuit verification instances, this method is greatly more efficient than BDD-based symbolic model checking, and compares favorably to some recent SAT-based model checking methods on positive instances.

Interpolation and SAT-based model checking

To alleviate the complex communication problems that arise as the number of on-chip components increases, network-on-chip (NoC) architectures have been recently proposed to replace global interconnects. In this paper, we first provide a general description of NoC architectures and applications. Then, we enumerate several related research problems organized under five main categories: Application characterization, communication paradigm, communication infrastructure, analysis, and solution evaluation. Motivation, problem description, proposed approaches, and open issues are discussed for each problem from system, microarchitecture, and circuit perspectives. Finally, we address the interactions among these research problems and put the NoC design process into perspective.

Outstanding Research Problems in NoC Design: System, Microarchitecture, and Circuit Perspectives

The large number of ReLU non-linearity operations in existing deep neural networks makes them ill-suited for latency-efficient private inference (PI). Existing techniques to reduce ReLU operations often involve manual effort and sacrifice significant accuracy. In this paper, we first present a novel measure of non-linearity layers' ReLU sensitivity, enabling mitigation of the time-consuming manual efforts in identifying the same. Based on this sensitivity, we then present SENet, a three-stage training method that for a given ReLU budget, automatically assigns per-layer ReLU counts, decides the ReLU locations for each layer's activation map, and trains a model with significantly fewer ReLUs to potentially yield latency and communication efficient PI. Experimental evaluations with multiple models on various datasets show SENet's superior performance both in terms of reduced ReLUs and improved classification accuracy compared to existing alternatives. In particular, SENet can yield models that require up to ~2x fewer ReLUs while yielding similar accuracy. For a similar ReLU budget SENet can yield models with ~2.32% improved classification accuracy, evaluated on CIFAR-100.

Learning to Linearize Deep Neural Networks for Secure and Efficient Private Inference

As the world collects more data, the electronics industry is demanding faster and more energy efficient supercomputers, but this is becoming an increasingly challenging goal as Moore's law nears its end. Superconducting electronics, and single flux quantum (SFQ) in particular, is a promising option for future exascale supercomputing. Nevertheless, timing uncertainty-represented by the inaccuracy of gates delays-renders the design of high-frequency clock distribution networks (CDN) to be one of the challenges that is impeding SFQ processors from attaining their full promised potential. As a radical solution to this challenge, the hierarchical chains of homogeneous clover-leaves clocking, (HC)
 2
 LC, was proposed. (HC)
 2
 LC uses an asynchronous CDN to provide the timing of a fully synchronous system, promising superior robustness over the conventional zero-skew clock trees with modest area and performance overheads. In this article, we propose algorithms that optimize the construction of the (HC)
 2
 LC network. We optimize both the insertion delay and the gates-assignment problem resulting in area reduction of 51%, and yield improvement of 166% compared to the unoptimized (HC)
 2
 LC. Moreover, we propose a placement-aware variation model, and we present a tool, the qHC
 2
LC, using both of which, we perform a complete comparison between zero-skew clock trees and (HC)
 2
 LC. Our simulations show that averaging over the ISCAS'85 benchmark circuits, at the same speed, and with an area overhead of 9%, (HC)
 2
 LC achieves 52% and 211% yield improvement over zero-skew trees at low and medium ranges of σ of gate delays, respectively.

Optimizing (HC)(2) LC, A Robust Clock Distribution Network For SFQ Circuits

In some applications, well-designed asynchronous systems can dramatically outperform their synchronous counterparts in terms of average speed. One recent example is the Revolving Asynchronous Intel Pentium Processor Instruction Decoder (RAPPID) which achieves 3 times higher average throughput than its comparable synchronous counterpart [103, 115]. Such systems must be highly concurrent and optimized for their average-case performance. Unfortunately, analyzing the performance of asynchronous systems is challenging, and there is an extreme lack of supporting CAD tools. This thesis presents two categories of performance analysis methodologies. The methods in the first category compute the theoretical (or exact) values of average performance metrics by modeling systems using Markov chains, and subsequently solving the models using Markovian analysis. The thesis developed several novel methods to attack the state explosion problem associated with Markovian analysis of large systems. The methods in the second category compute lower and upper bounds on performance metrics of systems that are modeled using stochastic timed Petri nets. The bounds are derived using finite net executions, and are evaluated using statistical methods. These methods do not require a state-level analysis, and thus can handle systems of very large size. As an example, a Petri net model of RAPPID with over 900 transitions and 500 places has been successfully analyzed. The resulting bounds are typically much sharper than using any other known method, and are in fact very close to the theoretical values. Moreover, the theory behind the bounding techniques provides a foundation for performance optimization of complex asynchronous circuits and systems. As one of their distinct features, the techniques in both categories are developed to handle arbitrarily distributed delays in order to increase the modeling power. All these techniques have been extensively tested and each represents the current state-of-the-art in its own respect. Due to the generality of the problems addressed, the potential applications of the work presented in this thesis are well beyond asynchronous circuits and systems. For instance, they are directly applicable to a wide class of discrete event systems such as embedded systems, database systems and security-oriented networks.

Performance analysis of asynchronous circuits and systems

The risk of soft errors due to radiation continues to be a significant challenge for engineers trying to build systems that can handle harsh environments. Building systems that are Radiation Hardened by Design (RHBD) is the preferred approach, but existing techniques are expensive in terms of performance, power, and/or area. This paper introduces a novel soft-error resilient asynchronous bundled-data design template, SERAD, which uses a combination of temporal and spatial redundancy to mitigate Single Event Transients (SETs) and upsets (SEUs). SERAD uses Error Detecting Logic (EDL) to detect SETs at the inputs of sequential elements and correct them via re-sampling. Because SERAD only pays the delay penalty in the presence of an SET, which rarely occurs, its average performance is comparable to the baseline synchronous design. We tested the SERAD design using a combination of Spice and Verilog simulations and evaluated its impact on area, frequency, and power on an open-core MIPS-like processor using a NCSU 45nm cell library. Our post-synthesis results show that the SERAD design consumes less than half of the area of the Triple Modular Redundancy (TMR), exhibits significantly less performance degradation than Glitch Filtering (GF), and consumes no more total power than the baseline unhardened design.

SERAD: Soft Error Resilient Asynchronous Design using a Bundled Data Protocol

The em integrated fan out optimization slack matching problem is the problem of jointly building fan out trees and slack matching the circuit. In particular, we insert a minimum number of asynchronous pipelined buffers to achieve a performance target while simultaneously ensuring the fan out count of all the nodes of the circuit is less than specified limits. Our result show that by solving the problem jointly up to 45% reduction in the total number of buffers can achieved compared to the state-of-the-art independent formulations.

Peter A. Beerel

Papers

Learning to Linearize Deep Neural Networks for Secure and Efficient Private Inference

Optimizing (HC)(2) LC, A Robust Clock Distribution Network For SFQ Circuits

Performance analysis of asynchronous circuits and systems

SERAD: Soft Error Resilient Asynchronous Design using a Bundled Data Protocol

Integrated Fanout Optimization and Slack Matching of Asynchronous Circuits