High leakage current in deep-submicrometer regimes is becoming a significant contributor to power dissipation of CMOS circuits as threshold voltage, channel length, and gate oxide thickness are reduced. Consequently, the identification and modeling of different leakage components is very important for estimation and reduction of leakage power, especially for low-power applications. This paper reviews various transistor intrinsic leakage mechanisms, including weak inversion, drain-induced barrier lowering, gate-induced drain leakage, and gate oxide tunneling. Channel engineering techniques including retrograde well and halo doping are explained as means to manage short-channel effects for continuous scaling of CMOS devices. Finally, the paper explores different circuit techniques to reduce the leakage power consumption.

Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits

Materials research plays a vital role in transforming breakthrough scientific ideas into next-generation technology. Similar to the way silicon revolutionized the microelectronics industry, the proper materials can greatly impact the field of plasmonics and metamaterials. Currently, research in plasmonics and metamaterials lacks good material building blocks in order to realize useful devices. Such devices suffer from many drawbacks arising from the undesirable properties of their material building blocks, especially metals. There are many materials, other than conventional metallic components such as gold and silver, that exhibit metallic properties and provide advantages in device performance, design flexibility, fabrication, integration, and tunability. This review explores different material classes for plasmonic and metamaterial applications, such as conventional semiconductors, transparent conducting oxides, perovskite oxides, metal nitrides, silicides, germanides, and 2D materials such as graphene. This review provides a summary of the recent developments in the search for better plasmonic materials and an outlook of further research directions.

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Alternative Plasmonic Materials: Beyond Gold and Silver

An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Semiconductor device, and manufacturing method thereof

The integration of materials having a high dielectric constant (high-kappa) into carbon-nanotube transistors promises to push the performance limit for molecular electronics. Here, high-kappa (approximately 25) zirconium oxide thin-films (approximately 8 nm) are formed on top of individual single-walled carbon nanotubes by atomic-layer deposition and used as gate dielectrics for nanotube field-effect transistors. The p-type transistors exhibit subthreshold swings of S approximately 70 mV per decade, approaching the room-temperature theoretical limit for field-effect transistors. Key transistor performance parameters, transconductance and carrier mobility reach 6,000 S x m(-1) (12 microS per tube) and 3,000 cm2 x V(-1) x s(-1) respectively. N-type field-effect transistors obtained by annealing the devices in hydrogen exhibit S approximately 90 mV per decade. High voltage gains of up to 60 are obtained for complementary nanotube-based inverters. The atomic-layer deposition process affords gate insulators with high capacitance while being chemically benign to nanotubes, a key to the integration of advanced dielectrics into molecular electronics.

http://nano.eecs.berkeley.edu/publications/Javey_NatMat_2004.pdf

High-κ dielectrics for advanced carbon- nanotube transistors and logic gates

High dielectrics for advanced carbon nanotube transistors and logic

A method of forming a trench isolation region. The method of the present invention comprises the steps of forming an opening in a semiconductor substrate, oxidizing the opening a first time, and then etching the oxidized opening with a wet etchant comprising HF. The opening is then oxidized a second time.

Shallow trench isolation technique

A leading edge 130 nm generation logic technology with 6 layers of dual damascene Cu interconnects is reported. Dual Vt transistors are employed with 1.5 nm thick gate oxide and operating at 1.3 V. High Vt transistors have drive currents of 1.03 mA//spl mu/m and 0.5 mA//spl mu/m for NMOS and PMOS respectively, while low Vt transistors have currents of 1.17 mA//spl mu/m and 0.6 mA//spl mu/m respectively. Technology design rules allow a 6-T SRAM cell with an area of 2.45 /spl mu/m/sup 2/, while array specific design rule give the densest SRAM reported to date, the 6-T cell has an area of only 2.09 /spl mu/m/sup 2/. Excellent yield and performance is demonstrated on a 18 Mbit CMOS SRAM.

A 130 nm generation logic technology featuring 70 nm transistors, dual Vt transistors and 6 layers of Cu interconnects

A leading edge 130 nm technology with 6 layers of Cu interconnects and 1.3 V operation has previously been presented (Tyagi et al., 2000). In this work, we enhance the previous technology with the following: transistor improvements which support a 60 nm gate dimension and increased drive current, improved 6-T SRAM device matching to allow low power and high performance operation from 0.7 to 1.4 V, and a 5% linear shrink to reduce the 6-T SRAM cell to 2.00 /spl mu/m/sup 2/ while still using 248 nm lithography. Saturation drive currents of 1.30 mA//spl mu/m for N-channel and 0.66 mA//spl mu/m for P-channel low VT devices are the highest reported to date. Excellent device short channel effects are obtained for the 60 nm gate length devices as measured by the 270 mV threshold voltage and <100 mV/V DIBL. These results have been achieved on both 200 and 300 mm wafers.

An enhanced 130 nm generation logic technology featuring 60 nm transistors optimized for high performance and low power at 0.7 - 1.4 V

A method of forming a trench isolation structure in a semiconductor substrate. After etching a trench into the semiconductor substrate, an oxide layer is formed within the trench. The surface of this oxide layer is subjected to a nitrogen plasma. Subsequently, another oxide layer is deposited over the nitrogen-rich surface of the first oxide layer. Deposition of this second oxide layer is accomplished by a chemical vapor deposition (CVD) process primarily using a reactant gas other than ozone.

Trench isolation process using nitrogen preconditioning to reduce crystal defects

A method of fabricating a field effect transistor with increased resistance to hot carrier damage is disclosed. An oxide is grown on the gate electrode. This oxide is strengthened by nitridation and anneal. After a lightly doped drain implant, a second side oxide and a conformal nitride layer are deposited. Then, the conformal nitride is anisotropically etched to form spacers for masking a high dose drain implant. An NMOS transitor fabricated with this process has been found to be forty percent less susceptible to hot carrier damage than a conventional lightly doped drain process. Also, this process has proven to be more manufacturable than one in which the side oxide is nitrided and re-oxidized.

Peter K. Moon

Papers

Shallow trench isolation technique

A 130 nm generation logic technology featuring 70 nm transistors, dual Vt transistors and 6 layers of Cu interconnects

An enhanced 130 nm generation logic technology featuring 60 nm transistors optimized for high performance and low power at 0.7 - 1.4 V

Trench isolation process using nitrogen preconditioning to reduce crystal defects

Method for fabricating a transistor with increased hot carrier resistance by nitridizing and annealing the sidewall oxide of the gate electrode