P
P. Nguyen
Researcher at Intel
Publications - 18
Citations - 1807
P. Nguyen is an academic researcher from Intel. The author has contributed to research in topics: PMOS logic & Integrated injection logic. The author has an hindex of 14, co-authored 18 publications receiving 1695 citations.
Papers
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Journal ArticleDOI
A 90-nm logic technology featuring strained-silicon
Scott E. Thompson,Mark Armstrong,C. Auth,Mohsen Alavi,M. Buehler,R. Chau,S. Cea,Tahir Ghani,G. Glass,T. Hoffman,Chia-Hong Jan,C. Kenyon,Jason Klaus,K. Kuhn,Z. Ma,B. McIntyre,Kaizad Mistry,Anand Portland Murthy,B. Obradovic,Ramune Nagisetty,P. Nguyen,Swaminathan Sivakumar,R. Shaheed,Lucian Shifren,B. Tufts,S. Tyagi,M. Bohr,Y. El-Mansy +27 more
TL;DR: In this paper, a leading-edge 90-nm technology with 1.2-nm physical gate oxide, 45-nm gate length, strained silicon, NiSi, seven layers of Cu interconnects, and low/spl kappa/CDO for high-performance dense logic is presented.
Proceedings ArticleDOI
A 90 nm logic technology featuring 50 nm strained silicon channel transistors, 7 layers of Cu interconnects, low k ILD, and 1 /spl mu/m/sup 2/ SRAM cell
Scott E. Thompson,Nidhi Anand,Mark Armstrong,C. Auth,B. Arcot,Mohsen Alavi,P. Bai,J. Bielefeld,Robert M. Bigwood,J. Brandenburg,M. Buehler,Stephen M. Cea,V. Chikarmane,C. H. Choi,R. Frankovic,Tahir Ghani,G. Glass,W. Han,Thomas Hoffmann,Makarem A. Hussein,P. Jacob,Ajay Jain,Chia-Hong Jan,Subhash M. Joshi,C. Kenyon,Jason Klaus,S. Klopcic,J. Luce,Z. Ma,B. McIntyre,Kaizad Mistry,Anand Portland Murthy,P. Nguyen,H. Pearson,T. Sandford,R. Schweinfurth,R. Shaheed,Swaminathan Sivakumar,M. Taylor,B. Tufts,Charles H. Wallace,P.-H. Wang,Cory E. Weber,Mark T. Bohr +43 more
TL;DR: In this paper, a leading edge 90 nm technology with 1.2 nm physical gate oxide, 50 nm gate length, strained silicon, NiSi, 7 layers of Cu interconnects, and low k carbon-doped oxide (CDO) for high performance dense logic is presented.
Proceedings ArticleDOI
A 130 nm generation logic technology featuring 70 nm transistors, dual Vt transistors and 6 layers of Cu interconnects
Sunit Tyagi,Mohsen Alavi,Robert M. Bigwood,T. Bramblett,J. Brandenburg,W. Chen,B. Crew,Makarem A. Hussein,P. Jacob,C. Kenyon,C. Lo,B. McIntyre,Z. Ma,Peter K. Moon,P. Nguyen,L. Rumaner,R. Schweinfurth,Swaminathan Sivakumar,M. Stettler,Scott E. Thompson,B. Tufts,J. Xu,Simon Yang,M. Bohr +23 more
TL;DR: In this paper, a leading edge 130 nm generation logic technology with 6 layers of dual damascene Cu interconnects is reported, where dual Vt transistors are employed with 1.5 nm thick gate oxide and operating at 1.3 V.
Proceedings ArticleDOI
MRAM as Embedded Non-Volatile Memory Solution for 22FFL FinFET Technology
Oleg Golonzka,Juan G. Alzate,Umut Arslan,M. Bohr,P. Bai,Justin S. Brockman,Buford Benjamin,Chris Connor,Nilanjan Das,Brian S. Doyle,Tahir Ghani,Fatih Hamzaoglu,Philip E. Heil,P. Hentges,Rownak Jahan,David L. Kencke,Blake C. Lin,M. Lu,M. Mainuddin,Mesut Meterelliyoz,P. Nguyen,Dmitri E. Nikonov,O'brien Kevin P,J.O Donnell,Kaan Oguz,Ouellette Daniel G,Joodong Park,Pellegren James,Conor P. Puls,Pedro A. Quintero,Tofizur Rahman,A. Romang,M. Sekhar,A. Selarka,M. Seth,Smith Andrew,Smith Angeline K,Liqiong Wei,Christopher J. Wiegand,Z. Zhang,Kevin J. Fischer +40 more
TL;DR: Embedded NVM technology presented here achieves 200°C 10-year retention capability combined with>106 cycle endurance and high die yield, and is demonstrated on 7.2Mbit arrays.
Proceedings ArticleDOI
A high performance 180 nm generation logic technology
Simon Yang,S. Ahmed,B. Arcot,R. Arghavani,P. Bai,S. Chambers,P. Charvat,Raymond E. Cotner,R. Gasser,Tahir Ghani,Makarem A. Hussein,Chia-Hong Jan,C. Kardas,J. Maiz,P. McGregor,B. McIntyre,P. Nguyen,Paul A. Packan,Ian R. Post,Swaminathan Sivakumar,Joseph M. Steigerwald,M. Taylor,B. Tufts,S. Tyagi,M. Bohr +24 more
TL;DR: In this article, a 180 nm generation logic technology has been developed with high performance 140 nm L/sub GATE/ transistors, six layers of aluminum interconnects and low/spl epsi/ SiOF dielectrics.