P
Peter Wright
Researcher at Stanford University
Publications - 45
Citations - 6838
Peter Wright is an academic researcher from Stanford University. The author has contributed to research in topics: Product (category theory) & Gate oxide. The author has an hindex of 23, co-authored 45 publications receiving 6405 citations.
Papers
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Thickness Limitations of Si02 Gate Dielectrics for
Peter Wright,Krishna C. Saraswat +1 more
TL;DR: In this article, the impact of gate leakage current on MOSFET performance has been examined and limits on gate oxide thickness for static and dynamic logic have been determined, and it has been found that leakage current is a greater problem for static logic than dynamic logic circuits.
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Comment, with reply, on 'Hot-electron hardened Si-gate MOSFET utilizing F implantation' by Y. Nishioka, et al
Peter Wright,Krishna C. Saraswat +1 more
TL;DR: The authors of the original paper were not, as they have claimed, the first to show the technique and benefits of implanting and diffusing fluorine as mentioned in this paper, but they did not make the claim attributed to them, and they defined their method and findings at length.
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Electrical characteristics and irradiation sensitivity of IGFETs with rapidly grown ultrathin gate dielectrics
TL;DR: In this paper, an n-channel insulated-gate field effect transistors (IGFETs) with gate insulators (50-60 AA) formed by rapid thermal processing (RTP) in O/sub 2/ and NH/sub 3/ ambients were reported.
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The Effect of Post-Growth Anneals on Nitroxide Films
TL;DR: In this paper, a post-oxidation annealing technique was introduced to improve the properties and long-term reliability of ultrathin (<100 A) MOS gate dielectrics, where after oxidation, nitridation is done in NH3 followed by a light reoxidation in O2 and then an inert anneal in Ar or N2.