The production and propagation of single-event transients in scaled metal oxide semiconductor (CMOS) digital logic circuits are examined. Scaling trends to the 100-nm technology node are explored using three-dimensional mixed-level simulations, including both bulk CMOS and silicon-on-insulator (SOI) technologies. Significant transients in deep submicron circuits are predicted for particle strikes with linear energy transfer as low as 2 MeV-cm/sup 2//mg, and unattenuated propagation of such transients can occur in bulk CMOS circuits at the 100-nm technology node. Transients approaching 1 ns in duration are predicted in bulk CMOS circuits. Body-tied SOI circuits produce much shorter transients than their bulk counterparts, making them more amenable to transient filtering schemes based on temporal redundancy. Body-tied SOI circuits also maintain a significant advantage in single-event transient immunity with scaling.

Production and propagation of single-event transients in high-speed digital logic ICs

Direct ionization from low energy protons is shown to cause upsets in a 65-nm bulk CMOS SRAM, consistent with results reported for other deep submicron technologies. The experimental data are used to calibrate a Monte Carlo rate prediction model, which is used to evaluate the importance of this upset mechanism in typical space environments. For the ISS orbit and a geosynchronous (worst day) orbit, direct ionization from protons is a major contributor to the total error rate, but for a geosynchronous (solar min) orbit, the proton flux is too low to cause a significant number of events. The implications of these results for hardness assurance are discussed.

Impact of Low-Energy Proton Induced Upsets on Test Methods and Rate Predictions

Experimental data are presented showing that low energy (<2 MeV) proton irradiation can upset exploratory 65 nm node, silicon-on-insulator circuits. Alpha particle SER data, modeling and simulation results provide a plausible mechanism. This work suggests that track structures need to be understood and effectively modeled, especially for small, modern devices.

Low-Energy Proton-Induced Single-Event-Upsets in 65 nm Node, Silicon-on-Insulator, Latches and Memory Cells

In this paper, lateral gate-all-around nano-sheet transistors (NSH-FETs) are explored from intrinsic performance to dc and ring oscillator (RO) benchmark compared with FinFETs and nanowire transistors (NW-FETs) for sub-7-nm node. The band structure calculated technology computer aided design results show comparable intrinsic performance to FinFETs at same channel cross section. On top of that, dc and RO are evaluated by taking into account electrostatics, parasitic components, and layout configurations. The NSH-FETs show an advantage in drive current with the NSH width but their RO performance is limited by the device capacitance. The multiple narrow NSH-FET shows ~5% higher drive current compared to the NW-FET at similar subthreshold swing, allowing heavier capacitive loaded circuit. In addition, NSH-FETs can provide the device design freedom from aggressive fin pitch scaling.

Device Exploration of NanoSheet Transistors for Sub-7-nm Technology Node

This document describes the radiation environments, physical mechanisms, and test philosophies that underpin radiation hardness assurance test methodologies. The natural space radiation environment is presented, including the contributions of both trapped and transient particles. The effects of shielding on radiation environments are briefly discussed. Laboratory radiation sources used to simulate radiation environments are covered, including how to choose appropriate sources to mimic environments of interest. The fundamental interactions of radiation with materials via direct and indirect ionization are summarized. Some general test considerations are covered, followed by in-depth discussions of physical mechanisms and issues for total dose and single-event effects testing. The purpose of this document is to describe why the test protocols we use are constructed the way they are. In other words, to answer the question: “Why do we test it that way”?

Radiation Hardness Assurance Testing of Microelectronic Devices and Integrated Circuits: Radiation Environments, Physical Mechanisms, and Foundations for Hardness Assurance

A comparative DC and AC performance evaluation between tri-gate FinFETs and gate-all-around nanowire FETs is carried out for potential sub-7nm technology node. The comparative analysis of the intrinsic and parasitic components using the classical drift-diffusion transport and quantization models indicates that a wider and thinner stacked nanosheet-type design can address the issues associated with conventional nanowire devices while demonstrating improved performance relative to FinFET. The optimization of the wire suspension region is found to be critical for Ieff-Ceff performance trade-offs.

Performance trade-offs in FinFET and gate-all-around device architectures for 7nm-node and beyond

Experimental and modeling results are presented on the critical charge required to upset exploratory 65 nm silicon-on-insulator (SOI) circuits. Using a mono-energetic, collimated, beam of particles the charge deposition was effectively modulated and modeled

Single-Event-Upset Critical Charge Measurements and Modeling of 65 nm Silicon-on-Insulator Latches and Memory Cells

Several major electron scattering mechanisms in tungsten (W) are evaluated using a combination of first-principles density functional theory, a Non-Equilibrium Green's Function formalism, and thin film Kelvin 4-point sheet resistance measurements. The impact of grain boundary scattering is found to be roughly an order of magnitude larger than the impact of defect scattering. Ab initio simulations predict average grain boundary reflection coefficients for a number of twin grain boundaries to lie in the range r = 0.47 to r = 0.62, while experimental data can be fit to the empirical Mayadas-Schatzkes model with a comparable but slightly larger value of r = 0.69. The experimental and simulation data for grain boundary resistivity as a function of grain size show excellent agreement. These results provide crucial insights for understanding the impact of scaling of W-based contacts between active devices and back-end-of-line interconnects in next-generation semiconductor technology.

Defect and grain boundary scattering in tungsten: A combined theoretical and experimental study

Physics-based modeling of the impact ionization process in silicon was performed to determine the time constants and radial distribution of electron-hole pairs after an /spl alpha/-particle strike. The radial distribution exhibited a Gaussian shape with a radius of approximately 50 nm. The impact ionization process took place over a period of less than approximately 500 fsec, implying time constants for use in semiconductor device simulations on the order of a few hundred fsec, a value much smaller than has been used in earlier device simulation work. Device simulations then show that the implication of using these shorter time constants is the creation of a higher concentration of electron-hole pairs at shorter times that cause stronger shunting effects for /spl alpha/-particle strikes between source and drain of MOS transistors.

Phil Oldiges

Papers

Low-Energy Proton-Induced Single-Event-Upsets in 65 nm Node, Silicon-on-Insulator, Latches and Memory Cells

Performance trade-offs in FinFET and gate-all-around device architectures for 7nm-node and beyond

Single-Event-Upset Critical Charge Measurements and Modeling of 65 nm Silicon-on-Insulator Latches and Memory Cells

Defect and grain boundary scattering in tungsten: A combined theoretical and experimental study

Theoretical determination of the temporal and spatial structure of /spl alpha/-particle induced electron-hole pair generation in silicon