P
Pier Andrea Francese
Researcher at IBM
Publications - 85
Citations - 1880
Pier Andrea Francese is an academic researcher from IBM. The author has contributed to research in topics: CMOS & Successive approximation ADC. The author has an hindex of 22, co-authored 76 publications receiving 1480 citations. Previous affiliations of Pier Andrea Francese include ETH Zurich & National Semiconductor.
Papers
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Journal ArticleDOI
A 3.1 mW 8b 1.2 GS/s Single-Channel Asynchronous SAR ADC With Alternate Comparators for Enhanced Speed in 32 nm Digital SOI CMOS
Lukas Kull,Thomas Toifl,Martin L. Schmatz,Pier Andrea Francese,Christian Menolfi,Matthias Braendli,Marcel Kossel,Thomas Morf,Toke Meyer Andersen,Yusuf Leblebici +9 more
TL;DR: An 8b 1.2 GS/s single-channel Successive Approximation Register (SAR) ADC is implemented in 32 nm CMOS, achieving 39.3 dB SNDR and a Figure-of-Merit (FoM) of 34 fJ per conversion step.
Proceedings ArticleDOI
22.1 A 90GS/s 8b 667mW 64× interleaved SAR ADC in 32nm digital SOI CMOS
Lukas Kull,Thomas Toifl,Martin L. Schmatz,Pier Andrea Francese,Christian Menolfi,Matthias Braendli,Marcel Kossel,Thomas Morf,Toke Meyer Andersen,Yusuf Leblebici +9 more
TL;DR: First CMOSADCs with at least 6b and conversion rates exceeding 20GS/s were presented, proving that interleaved SAR ADCs are an optimal choice for high-speed ADCs with moderate resolution.
Proceedings ArticleDOI
4.7 A sub-ns response on-chip switched-capacitor DC-DC voltage regulator delivering 3.7W/mm 2 at 90% efficiency using deep-trench capacitors in 32nm SOI CMOS
Toke Meyer Andersen,Florian Krismer,Johann W. Kolar,Thomas Toifl,Christian Menolfi,Lukas Kull,Thomas Morf,Marcel Kossel,Matthias Brandli,Peter Buchmann,Pier Andrea Francese +10 more
TL;DR: On-chip switched-capacitor converters have gained increasing popularity for this application due to their ease of integration using only transistors and capacitors readily available in the chosen technologies.
Journal ArticleDOI
A 1.8 V 1.0 GS/s 10b Self-Calibrating Unified-Folding-Interpolating ADC With 9.1 ENOB at Nyquist Frequency
Robert Callaghan Taft,Pier Andrea Francese,M.R. Tursi,Ols Hidri,A. MacKenzie,T. Hoehn,P. Schmitz,Heinz Werker,A. Glenny +8 more
TL;DR: An advance in folding-interpolating analog-to-digital converters (ADCs) is demonstrated which simplifies their extension to higher resolution by building the converter out of identical but scaled pipelined cascaded folding stages.
Proceedings Article
A 2.6 mW/Gbps 12.5 Gbps RX With 8-Tap Switched-Capacitor DFE in 32 nm CMOS
Thomas Toifl,Christian Menolfi,Michael Ruegg,Robert Reutemann,Daniel M. Dreps,Troy J. Beukema,Andrea Prati,Daniele Gardellini,Marcel Kossel,Peter Buchmann,Matthias Brandli,Pier Andrea Francese,Thomas Morf +12 more
TL;DR: It is shown that the transceiver power and the effect of high-frequency transmit jitter can be reduced by implementing a linear equalizer only on the receive side and avoiding a transmit feed-forward equalizer (TX-FFE).