T
Thomas Morf
Researcher at IBM
Publications - 165
Citations - 3633
Thomas Morf is an academic researcher from IBM. The author has contributed to research in topics: CMOS & Jitter. The author has an hindex of 29, co-authored 158 publications receiving 3212 citations. Previous affiliations of Thomas Morf include GlobalFoundries & École Polytechnique Fédérale de Lausanne.
Papers
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Journal ArticleDOI
A 3.1 mW 8b 1.2 GS/s Single-Channel Asynchronous SAR ADC With Alternate Comparators for Enhanced Speed in 32 nm Digital SOI CMOS
Lukas Kull,Thomas Toifl,Martin L. Schmatz,Pier Andrea Francese,Christian Menolfi,Matthias Braendli,Marcel Kossel,Thomas Morf,Toke Meyer Andersen,Yusuf Leblebici +9 more
TL;DR: An 8b 1.2 GS/s single-channel Successive Approximation Register (SAR) ADC is implemented in 32 nm CMOS, achieving 39.3 dB SNDR and a Figure-of-Merit (FoM) of 34 fJ per conversion step.
Journal ArticleDOI
Polymer-Waveguide-Based Board-Level Optical Interconnect Technology for Datacom Applications
Roger Dangel,C. Berger,R. Beyeler,Laurent Dellmann,M. Gmur,R. Hamelin,Folkert Horst,Tobias Lamprecht,Thomas Morf,Stefano S. Oggioni,Mauro Spreafico,Bert Jan Offrein +11 more
TL;DR: The fabrication and characterization of board-integrated optical low-loss polymer waveguides that are compatible with printed circuit board (PCB) manufacturing processes are reported on, and the fully passive alignment technique, superseding time-consuming active positioning of components and connectors is explained.
Proceedings ArticleDOI
A 28-Gb/s 4-Tap FFE/15-Tap DFE Serial Link Transceiver in 32-nm SOI CMOS Technology
John F. Bulzacchelli,Christian Menolfi,Troy J. Beukema,Daniel W. Storaska,Juergen Hertle,David R. Hanson,Ping-Hsuan Hsieh,Sergey V. Rylov,D. Furrer,Daniele Gardellini,Andrea Prati,Thomas Morf,V. Sharma,R. Kelkar,Herschel A. Ainspan,William R. Kelly,L. R. Chieco,G. A. Ritter,J. A. Sorice,Jon D. Garlett,Robert Callan,Matthias Brandli,P. Buchmann,Marcel Kossel,Thomas Toifl,Daniel J. Friedman +25 more
TL;DR: This paper describes a 28Gb/s serial link transceiver featuring a source-series terminated (SST) driver topology with twice the speed of existing designs, a two-stage peaking amplifier with capacitively-coupled parallel input stages and active feedback, and a 15-tap DFE.
Journal ArticleDOI
A T-Coil-Enhanced 8.5 Gb/s High-Swing SST Transmitter in 65 nm Bulk CMOS With $≪ -$ 16 dB Return Loss Over 10 GHz Bandwidth
Marcel Kossel,Christian Menolfi,Jonas R. Weiss,P. Buchmann,G. von Bueren,L. Rodoni,Thomas Morf,Thomas Toifl,Martin L. Schmatz +8 more
TL;DR: A source-series-terminated (SST) transmitter in a 65 nm bulk CMOS technology with duty-cycle restoration capability of 5x, and the common-mode voltage noise is below 10 mV rms for high-, mid- and low-level terminations.
Journal ArticleDOI
A low-power 20-GHz 52-dB/spl Omega/ transimpedance amplifier in 80-nm CMOS
TL;DR: In this article, a transimpedance amplifier (TIA) for a low-power, short-distance, high-density fiber-optic interconnect communication system is described.