Matthias Brandli

TL;DR: This paper describes a 28Gb/s serial link transceiver featuring a source-series terminated (SST) driver topology with twice the speed of existing designs, a two-stage peaking amplifier with capacitively-coupled parallel input stages and active feedback, and a 15-tap DFE.

TL;DR: On-chip switched-capacitor converters have gained increasing popularity for this application due to their ease of integration using only transistors and capacitors readily available in the chosen technologies.

TL;DR: In this article, the design and implementation of on-chip switched capacitor converters in deep submicron technologies is described, and the measured performance of a 2 : 1 voltage conversion ratio switched capacitor converter implemented in 32nm SOI CMOS technology with 1.8V input voltage results in a power density of 4.6W/mm2 at 86% efficiency when operated at a switching frequency of 100MHz.

TL;DR: It is shown that the transceiver power and the effect of high-frequency transmit jitter can be reduced by implementing a linear equalizer only on the receive side and avoiding a transmit feed-forward equalizer (TX-FFE).

TL;DR: A 64-Gb/s high-sensitivity non-return to zero receiver (RX) data-path is demonstrated in the 14-nm-bulk FinFET CMOS technology to achieve high sensitivity, which incorporates a transimpedance amplifier whose gain and bandwidth are co-optimized with a 1-tap decision feedback equalization (DFE).