Due to latch-up issue, the main problem of silicon-controlled rectifier (SCR) for power supply clamps in on-chip ESD protection is its inherent low holding voltage, especially in high-voltage applications. In this paper, we proposed a MOS-inside SCR (MISCR) showing nearly no snapback character and good ESD robustness, which is qualified for on-chip power clamp ESD protection. The stacked device achieves a series of triggering and holding voltage by altering the stacking number, which can also be used for the high voltage ESD power supply clamp applications.

Novel silicon-controlled rectifier (SCR) for digital and high-voltage ESD power supply clamp

A novel electrostatic discharge protection device gate-grounded nMOS (GGnMOS) incorporated silicon-controlled rectifier (GGISCR) is proposed in this paper. With a distinguished feature of an imbedded floating P+ region, the GGISCR is demonstrated to be superior to the conventional low voltage triggered SCR and GGnMOS in terms of high area efficiency and high holding voltage. The operational mechanism of GGISCR device is discussed in detail, and the effect of floating P+ region on the GGISCR’s $I$ – $V$ characteristics is analyzed via TCAD simulation results as well.

Design and Analysis of an Area-Efficient High Holding Voltage ESD Protection Device

Due to the snapback holding voltage of high-voltage (HV) nMOS smaller than the maximum operating voltage, the traditional power-rail electrostatic discharge (ESD) clamp circuit implemented with such HV nMOS suffered latchup-like failure in a touch panel control IC after the system-level ESD test. A modified design on the power-rail ESD clamp circuit is proposed and verified in an HV CMOS process with 12 V double-diffused drain MOS device. With the holding voltage greater than the maximum operating voltage of 12 V, the touch panel equipped with the modified control IC can successfully pass the system-level ESD test of ±15 kV in the air-discharge test mode to meet the level 4 of IEC 61000-4-2 industry specification.

ESD Protection Design for Touch Panel Control IC Against Latchup-Like Failure Induced by System-Level ESD Test

Modelling of working parameters of Gd and FeRh nanoparticles for magnetic hyperthermia

In this paper, the detailed characterizations of the lateral insulated-gate bipolar transistor (LIGBT) for the electro- static discharge (ESD) protection of power ICs are presented. Compared with the conventional lateral DMOS with the same structure except for the anode doping type, the LIGBT shows lower triggering voltage, faster voltage-clamping speed, and much higher ESD robustness. Experimental results demonstrate that the LIGBT with runway layout achieves excellent thermal breakdown current of more than 10 A with 250-μm device width. The high ESD performance enables the LIGBT to be used as a promising ESD protection device in the power ICs.

The Investigation of Electrothermal Characteristics of High-Voltage Lateral IGBT for ESD Protection

A silicon-controlled rectifier (SCR)-incorporated BJT with high holding voltage is developed for electrostatic discharge (ESD) protection in a 0.6 μm high-voltage 10 V process. This device consists simply of a floating P+ diffusion incorporated in a parasitic NPN BJT. A robust 6-7 kV ESD threshold and high-latchup-immune holding voltage of 15-18 V can be achieved by layout optimization of the NPN-N+ -collector to floating P+ -diffusion spacing and the floating P+ diffusion width. It can be equivalently regarded as parallel connection of an incorporated PNPN SCR part and an NPN BJT part. The incorporated SCR part is further composed of a parasitic SCR in series with a reverse-biased PN diode formed by the floating P+ region and N-well. The further analysis shows that the floating P+ diffusion is the key part of this SCR-incorporated BJT. The parasitic reverse-biased PN diode sustains most of the high holding voltage. The parasitic NPN BJT plays a major role in ESD current conduction, while the incorporated SCR in series with the reverse-biased PN diode is the secondary conduction path.

An SCR-Incorporated BJT Device for Robust ESD Protection With High Latchup Immunity in High-Voltage Technology

This paper develops optimization between electrostatic discharge (ESD) and latchup characteristics for a silicon-controlled rectifier (SCR)-incorporated Bipolar Junction Transistor (BJT) in a 0.18- $\mu \text{m}$ , 3.3 V process. This device is composed of a floating pMOSFET embedded in a parasitic n-well/p-sub/n+ region BJT structure. The floating pMOS gate is further coupled with an RC network for controlling its switching. The floating pMOS could increase the effective width of its floating p+ region to enhance ESD robustness during ESD zapping events, whereas maintain its floating p+ region narrower during IC operation situation. With the optimized structure dimensions, this device can reach transmission-line pulse second breakdown current 6 A, ESD/ human-body model over 8 kV, which are the same as those of an SCR, and its latchup trigger current is at least 1.9 times greater.

ESD and Latchup Optimization of an Embedded-Floating-pMOS SCR-Incorporated BJT

This work presents a novel gated- diode SCR-incorporated BJT (SIB) structure for ESD protection purpose. A gated diode built in the SIB structure modulates reverse-biased P+ / N-well diode for better junction breakdown control. This device could achieve high TLP second breakdown current /ESD threshold close to that of an SCR, very high holding voltage, and reduced trigger voltage, as well as excellent latchup immunity.

A Gated-Diode ESD SCR-Incorporated BJT for Reversed Floating P⁺ Junction Modulation

An SCR-buried BJT with a high holding voltage is developed for ESD protection in a 0.6 µm high voltage 10V process. This device simply consists of a floating P+ diffusion buried in a parasitic NPN BJT. A robust 6∼7KV ESD threshold and high-latchup-immune 15∼18V holding voltage can be achieved by layout optimization of the anode-to-floating- P+-diffusion spacing and this P+ diffusion width.

A SCR-buried BJT device for robust ESD protection with high latchup immunity in high-voltage technology

An SCR-incorporated BJT for latchup and ESD optimization is developed in a 0.18μm-3.3V process. This device simply consists of a floating P+ region in a parasitic NPN BJT. Its optimized second breakdown current exceeds 80% that of an SCR and latchup triggering current is 2~4 times greater.

Quo-Ker Chen

Papers

An SCR-Incorporated BJT Device for Robust ESD Protection With High Latchup Immunity in High-Voltage Technology

ESD and Latchup Optimization of an Embedded-Floating-pMOS SCR-Incorporated BJT

A Gated-Diode ESD SCR-Incorporated BJT for Reversed Floating P⁺ Junction Modulation

A SCR-buried BJT device for robust ESD protection with high latchup immunity in high-voltage technology

A high latchup - Immune ESD protection SCR-incorporated BJT in deep submicron technology