Showing papers in "IEEE Transactions on Device and Materials Reliability in 2021"
TL;DR: In this article, the authors illustrate the various fast charging techniques that are being used to charge the lithium-ion batteries in electric vehicles and compare them in terms of the charging time, the charging efficiency, and battery life.
Abstract: The objective of this article is to illustrate the various fast charging techniques that are being used to charge the lithium-ion batteries in electric vehicles. Various charging protocols such as constant current, constant voltage, constant current constant voltage, multistage constant current, varying current method, pulse charging methods are critically reviewed and explained in their broader perspective of fundamental concepts to their modeling/simulation. Amongst, the constant current constant voltage charging approach is considered as a benchmark for other charging protocols in terms of the charging time, the charging efficiency, and battery life. A critical comparison among the various charging methods mentioned above are discussed and possible future research directions in the design and development of new fast charging techniques have been proposed based on the commercial and societal demands.
37 citations
TL;DR: In this article, the ON-state gate current characterization of Schottky gate p-GaN capped AlGaN/GaN high-electron-mobility transistors on two distinct gate processes is presented.
Abstract: We present detailed ON-state gate current characterization of Schottky gate p-GaN capped AlGaN/GaN high-electron-mobility transistors (HEMTs) on two distinct gate processes. The threshold voltage is monitored from $10~\mathrm {\mu }\text{s}$ up to 100 s under positive gate bias stress and during recovery. The threshold voltage stability is affected by the balance between hole and electron current in the gate stack. More specifically, devices with uniform hole conduction across the p-GaN gate area demonstrate stable threshold voltage behavior up to $V_{g}=5\,\mathrm {V}$ , whereas devices with a dominating gate perimeter electron conduction demonstrate larger instabilities. Finally, the threshold voltage stability during OFF-state pulsed stress is investigated and correlated to the excess gate-to-drain charge extracted from capacitance curves.
25 citations
TL;DR: In this paper, a new metal-semiconductor field effect transistor (MESFET) is introduced by amending the carrier distribution in the active regions of the device for radio frequency applications (RF).
Abstract: In this article, a new metal-semiconductor field-effect transistor (MESFET) is introduced by amending the carrier distribution in the active regions of the device for radio frequency applications (RF). A quasi-two-dimensional material beta gallium oxide ( ${\beta }$ -Ga2O3) semiconductor is used as a fundamental material. To amend the carrier distribution, a tunnel diode (TD- ${\beta }$ GO) is employed at the bottom of the source and the channel regions in the buried oxide (BOX) layer of MESFET. In our work, parameters such as the breakdown voltage, the self-heating effect, the kink effect, the parasitic capacitance, the power gains, the noise figure, and the carrier’s concentration are obtained and compared with the conventional structure. As a result of employing the tunnel diode, the TD- ${\beta }$ GO MESFET has better characteristics in comparison with the C- ${\beta }$ GO MESFET though the drain current at the saturation region in the TD- ${\beta }$ GO structure is reduced.
19 citations
TL;DR: In this article, two ternary SRAM cells are proposed with a lower delay than their predecessor, which use an improved inverter, which is a fundamental building block of SRAMs.
Abstract: In this article, two ternary SRAMs are proposed with a lower delay than their predecessor. Both proposed SRAMs use an improved inverter, which is a fundamental building block of SRAMs. Due to this improvement, the speed of storing/retrieving data to/from the SRAM cells increased. The first proposed ternary SRAM cell uses different terminals for read and write operations to avoid the read disturb problem. The second proposed SRAM cell does not require an additional middle voltage (0.45V) to store ternary ‘1’. The first ternary SRAM cell requires a ternary sense amplifier to detect all the ternary level voltages, whereas the second ternary SRAM cell uses a simple two-level voltage detection sense amplifier. Further to observe the robustness of the proposed SRAM cells, Monte-Carlo analysis (process variation) was conducted over average power consumption, delay, power delay product (PDP), and static noise margin (SNM) by varying the diameter of the carbon nanotube and length of the channel.
17 citations
TL;DR: The results of the comprehensive Monte-Carlo simulations demonstrate that the proposed approach is more robust to process, voltage, and temperature variations as compared to their previous counterparts, and has lower error rates than its state-of-the-art counterparts.
Abstract: Radiation vulnerability and high power density are critical challenges in modern CMOS processors. Spin-based devices like magnetic tunnel junction (MTJ) are among the promising alternatives for addressing these challenges thanks to their fascinating properties such as radiation immunity, non-volatility, high endurance, and compatibility with the CMOS fabrication process. Utilizing the fascinating non-volatile property of the MTJ device, a high-performance, and energy-efficient soft error immune retention latch, and a high-reliable non-volatile flip-flop (FF) are proposed in this paper. Thanks to the single event upset (SEU) immunity, the proposed circuits are applicable in designing highly reliable processors, especially in applications like aerospace systems, where immunity to radiation induced soft errors is very critical. Because of the innovative design of the proposed approach, the MTJ switching delay does not affect the performance of the proposed latch. The simulation results indicate that the proposed latch offers lower delay, power consumption, and power delay product (PDP) than the state-of-the-art designs. The results of the comprehensive Monte-Carlo simulations also demonstrate that the proposed approach is more robust to process, voltage, and temperature variations as compared to their previous counterparts. This is because our designs do not use a pre-charge sense amplifier (PCSA) to read the data stored in the MTJs, and hence, the proposed designs have lower error rates. Furthermore, the transient impact of the particle strikes on the internal nodes is not transferred to the output node of the proposed circuits. The proposed design also has a significantly shorter output recovery time compared to its state-of-the-art counterparts.
14 citations
TL;DR: In this article, a radiation-hardened by design (RHBD) SRAM bit-cell is proposed based on the polarity upset mechanism of SEUs, and the proposed bit cell's sensitive area is 128% lower with respect to the recently reported state-of-the-art RHBD RSP14T bit-cells.
Abstract: Static Random Access Memory (SRAM) is primarily used as a memory storage element, which is susceptible to radiation-induced Single Event Upsets (SEUs). Hence, a robust SRAM bit-cell design is primarily a difficult task to address the space radiation environment. Furthermore, as the transistor’s size moves into nanometer regimes, a new challenge like Single Event Multiple Effects (SEME’s) evolved in SRAMs. SEME’s make the design of SRAM a serious challenge. In this article, a novel Radiation Hardened By Design (RHBD) SRAM bit-cell is proposed based on the polarity upset mechanism of SEUs. This work shows that the proposed RHBD14T SRAM bit-cell is SEU immune and delivers higher SEME critical charge than state-of-the-art RHBD SRAM bit-cells. The Monte Carlo (MC) simulations further show that the proposed RHBD14T SRAM delivers the lower Probability of Failure when compared to reported RHBD SRAM cells. Consequently, the proposed bit cell’s sensitive area is 128% lower with respect to the recently reported state-of-the-art RHBD RSP14T SRAM bit-cells.
12 citations
TL;DR: In this article, a glass substrate was used in the design of a fan-out wafer-level package (FO-WLP) and simulations were conducted to predict the reliability of the solder joints.
Abstract: In recent years, the use of fan-out packaging solutions has boomed in semiconductor-related fields. There are primarily two versions used for mass production: wafer level and panel level. In this research, a glass substrate was used in the design of a fan-out wafer-level package (FO-WLP) and simulations were conducted to predict the reliability of the solder joints. The advantages of glass substrates are their excellent electrical properties, good mechanical rigidity, flatness, and adjustable coefficient of thermal expansion. To verify the robustness of the simulations, a FO-WLP test vehicle was designed, manufactured, and tested under JEDEC thermal cycling condition. In this study, the simulation results were used in an empirical equation to estimate the reliability of the FO-WLP under accelerated thermal-cycling conditions. After simulation validated by experiments, parametric simulations of different design factors can be performed. Using this methodology, we developed a reliable finite element analysis procedure. Thus, structural optimization of the FO-WLP was possible via simulations using various design factors to improve its reliability. The simulation results indicate that a suitable combination of upper, lower pad sizes and the thickness of buffer layer could significantly enhance the reliability life of FO-WLP, and that designers should devote greater attention to these factors to achieve better long-term reliability performance.
11 citations
TL;DR: In this article, a method of monitoring the aging state of bond wire in SiC MOSFET module using on-state drain-source voltage (OSDSV) separation technique is proposed.
Abstract: Bond wire aging is a universal failure form of silicon carbide metal-oxide-semiconductor field-effect transistor (SiC MOSFET) module. Real-time condition monitoring of bond wire is an important guarantee for the stable operation of power electronics system. In this article, a method of monitoring the aging state of bond wire in SiC MOSFET module using on-state drain-source voltage (OSDSV) separation technique is proposed. Firstly, the temperature dependence of the conduction circuit resistance from drain terminal to source terminal in SiC MOSFET module is analyzed to obtain the temperature characteristics of the OSDSV. Secondly, the resistance of the package structure in SiC MOSFET module is extracted, and the OSDSV is divided into two parts: the package structure voltage and the chip OSDSV, and the analytical model for estimating the junction temperature of SiC MOSFET module in the healthy state is acquired. Finally, the package structure voltage is employed to monitor the aging degree of bond wire in SiC MOSFET module, and the flow chart of aging diagnosis of bond wire is established. The proposed method can accurately identify the failure state of bond wire lift-off. Theoretical and experimental results prove that the method is feasible.
11 citations
TL;DR: In this article, the effects of wiring density and solder pillar structure on chip-package interaction (CPI) for advanced Cu/low k mixed-signal chips were investigated.
Abstract: Multilevel finite element analysis (FEA) was used to study the effects of wiring density and solder pillar structure on chip-package interaction (CPI) for advanced Cu/low k mixed-signal chips. The mixed signal chip has analog and digital wiring designs with different metal densities, incorporating extreme low-k (ELK), low-k (LK) and oxide dielectrics in 10 wiring layers. The results are compared with uniform signal chips with uniform metal density on each wiring layer. The first principal stress was found to increase by 1.5 to 3x in the mixed signal chip between the analog and the isolation channel of the ELK and LK layers due to the different wiring density. In addition, the energy release rate (ERR) was significantly increased to reach a critical ERR ratio higher than 1 to drive interfacial delamination, raising serious chip-package interaction (CPI) reliability concern for the mixed signal chip. The results were attributed to the Dundurs effect due to the material mismatch and the nonuniform metal density in the mixed signal chip. In the study of the pillar structure effect, intermetallic compound (IMC) growth was found to be important and can substantially increase the critical ERR ratio to degrade the CPI reliability of the mixed signal chip.
11 citations
TL;DR: In this paper, the effect of variations in solder pad and trace design on the fatigue durability of copper traces was examined and a set of compatible fatigue model constants that best fit the failure behavior observed in the tests were established.
Abstract: While solder interconnects tend to be the focus of reliability studies in electronics, increased exposure to flexural loads and the use of stiffer (higher density) packages are raising concern regarding the fatigue failure of copper metallization (traces and solder pads) on printed circuit boards To better understand the failure risks of copper trace, experiments examining the effect of variations in solder pad and trace design on the fatigue durability of copper traces were conducted Experiments were also conducted to determine the impact of assembly variations, presence of surface finish, solder mask, and assembled components, on the fatigue durability of the traces The durability data collected from the experiment was used in conjunction with the finite element analysis estimated critical trace strain ranges to develop a set of compatible fatigue model constants that best fit the failure behavior observed in the tests Finally, the established fatigue life model constants were validated with additional tests conducted at different load level The predicted cycles to failure compared well with the experimental cycles to failure
10 citations
TL;DR: In this paper, an Eyring model is proposed to improve the prediction of lumen maintenance life under different thermal-electrical conditions, and a method to predict lumen depreciation trend for different operating conditions based on the Eyring Model and regression approach is established.
Abstract: The lifetime of light-emitting diodes (LEDs) is highly dependent on usage conditions such as operating temperature and drive current. It is costly and impractical to test the LEDs on every usage condition. Previous studies used the Arrhenius equation and Black’s model to investigate the relationship of operating temperature, drive current and lumen maintenance life. However, they are found to be less accurate for certain conditions. The study aims to improve the prediction of lumen maintenance life under different thermal-electrical conditions. The Eyring model is proposed in this study. The model parameters are determined by regression approach, which provides the goodness of fit of the prediction model as well as the prediction interval. Furthermore, a method to predict lumen depreciation trend for different operating conditions based on the Eyring model and regression approach is established. As a result, the Eyring model produced higher prediction accuracy compared to Arrhenius equation and Black’s model.
TL;DR: In this paper, the authors train and estimate the performance of an IMPLY-based implementation of a multilayer perceptron (MLP) BNN and highlight its main reliability challenges by using a physics-based RRAM compact model calibrated on three RRAM technologies.
Abstract: Resistive Random access memory (RRAM) devices together with the material implication (IMPLY) logic are a promising computing scheme for realizing energy efficient reconfigurable computing hardware for edge computing applications. This approach has been recently shown to enable the in-memory implementation of Binarized Neural Networks. However, an accurate analysis of the performance achieved on a real classification task are still missing. In this work, we train and estimate the performance of an IMPLY-based implementation of a multilayer perceptron (MLP) BNN and highlight its main reliability challenges by using a physics-based RRAM compact model calibrated on three RRAM technologies from the literature. We then show how the smart IMPLY (SIMPLY) architecture solves the reliability issues of conventional IMPLY architectures and compare its performance with respect to conventional solutions considering different parallelization degree. The worst-case energy estimates for an inference task performed on the trained network, show that the SIMPLY implementation results in a >46 energy-delay-product (EDP) improvement with respect to a conventional low-power embedded system implementation.
TL;DR: In this paper, a junctionless enhancement-type field effect transistor based pH sensor is proposed and fabricated through low-cost bulk CMOS aligned process, which consists of uniformly ex-situ doped p-type polySi.
Abstract: In this article, a junctionless enhancement-type field-effect-transistor based pH sensor is proposed and fabricated through low-cost bulk CMOS aligned process. The thin device layer consists of uniformly ex-situ doped p-type polySi, yielding a junctionless doping profile throughout the active region. A thin $Al_{2}O_{3}$ layer is deposited through atomic layer deposition as a sensing membrane, providing high site binding density for pH solutions. The effect of channel width ( $W_{si}$ ) ranging from 5 to $15~\mu \text{m}$ on threshold voltage and drain current sensitivities ( $\frac {\triangle {V_{th}}}{\triangle {pH}}$ , $\frac {\triangle {I_{d}}}{I_{d}}$ ) respectively, have been investigated for different pH buffer solutions. For $W_{si}$ of $5~\mu \text{m}$ , a maximum $\frac {\triangle {V_{th}}}{\triangle {pH}}$ sensitivity of 66.7mV/pH and current sensitivity of 98.9% was observed. Further, the drain current of $\simeq ~65$ nA at $V_{gs} = 0\text{V}$ and $V_{ds} = -4\text{V}$ , yields low leakage operation of the proposed sensor. Furthermore, the repeatability of the proposed sensor is demonstrated by repeating the drain current measurements thrice with an interval of 10 minutes between corresponding measurements. A maximum shift of 30.9% among all measurements at pH = 6 which corresponds to $\sim 0.1 \mu \text{A}$ was observed, implying excellent repeatability of the proposed sensor.
TL;DR: The results show that the current densities in the STT arrays can be large enough to cause EM failures in the signal lines with running realistic workloads and that these failures are highly workload-dependent.
Abstract: Electromigration (EM) has emerged as a major reliability concern for interconnects in advanced technology nodes. Most of the existing EM analysis works focus on the power lines. There exists a limited amount of work which analyzes EM failures in the signal lines. However, various emerging spintronic-based memory technologies such as the Spin Transfer Torque Magnetic Random Access Memory (STT-MRAM) and the Spin Orbit Torque Magnetic Random Access Memory (SOT-MRAM) have high current densities as compared to the conventional Static Random Access Memory (SRAM). These high current densities can lead to EM failures in the signal lines such as bit-line (BL) of these memories. Furthermore, these signal lines have workload-dependent stress as opposed to the conventional DC stress of power distribution networks. In this work, we model the EM failures in the BL of a typical STT memory array with realistic workloads. The analysis is based on physics-based EM model, which is calibrated based on industrial measurement data. The results show that the current densities in the STT arrays can be large enough to cause EM failures in the signal lines with running realistic workloads and that these failures are highly workload-dependent.
TL;DR: The trained model provides high accuracy test results within 1 % error, showing the possibility to expedite failure analysis cycle via machine learning.
Abstract: As Fin Field Effect Transistor (FinFET) scales aggressively, even a single point defect becomes a source of performance variability. The point defect is inevitably introduced not only by process damage such as epitaxial growth and ion implantation but also by cosmic rays. Technology computer-aided design (TCAD) is able to simulate the characteristics of the device with the defect. In this work, a machine learning algorithm is tested if it can reproduce the TCAD results. The impact of point defect in bulk FinFET is used as test vehicle to validate the machine-learning algorithm. TCAD is used first to generate a massive number of current-voltage characteristics dataset. The TCAD dataset is then exclusively divided into groups for machine learning training, validation and test. The trained model provides high accuracy test results within 1 % error, showing the possibility to expedite failure analysis cycle via machine learning.
TL;DR: In this article, the impact of the interface layer on charge trapping and polarization switching at multiple temperatures is investigated, and the relationship between the interfacing layer and the subsequently deposited ferroelectric layers' effective permittivity is demonstrated.
Abstract: The impact of the interface layer on charge trapping and polarization switching at multiple temperatures is investigated. At high temperatures, a ferroelectric field effect transistor with a metal-ferroelectric-insulator-semiconductor (MFIS) gate-stack shows conventional electron-trapping dominated PBTI (i.e., $\Delta \text{V}_{\mathrm{ t}} > 0$ ), whereas at room temperature, negative threshold voltage shifts ( $\Delta \text{V}_{\mathrm{ t}}$ ) are observed. We demonstrate the relationship between the interface layer and the subsequently deposited ferroelectric layers’ effective permittivity: higher permittivity, consistent with a higher tetragonal phase/lower orthorhombic phase content, is noted when the ferroelectric layer is deposited on hydrogen-terminated silicon. In contrast, an anomalous BTI, consistent with a higher orthorhombic phase content, is observed at lower temperatures when the ferroelectric layer is deposited on oxygen-rich surfaces (SiO2, SiON).
TL;DR: In this article, a push-pull pflash cell was proposed, which combined the advantages of indirect coupling and radiation-hardening, and it was successfully fabricated using 90 nm technology through the indirect coupling of the floating gate.
Abstract: The base component of radiation-hardened flash-based field-programmable gate arrays (FPGAs) is a reconfigurable memory cell, which is reliable and has high driving current A novel push-pull pflash cell was proposed in this article, which combined the advantages of indirect coupling and radiation-hardening The proposed device consisted of two 2T-flash transistors and a pMOS transistor The push-pull pflash cell was successfully fabricated using 90 nm technology Through the indirect coupling of the floating gate (FG), the proposed push-pull pflash cell overcame the interference found in sense-switch pflash cells Compared to conventional sense-switch pflash cells, the proposed push-pull pflash cell had superior driving current, reliability, and radiation-hardening Band-to-band tunneling-induced hot-electron (BBHE) programming was used to realize ON state, while Fowler-Nordheim (FN) erasing was used to realize OFF state in the proposed device The electrical properties of both states were characterized The ON-state driving current and OFF-state leakage current were shown to be consistent The uniformity of driving current under −12 V was below 3% The proposed device was capable of being programmed/erased cyclically over 10,000 times, and it had a 10-year lifespan with ON/OFF-state stress at 25°C Additionally, the proposed device was tolerant of total ionizing dose (TID) over 150 Krad(Si) The purposed push-pull pflash cell was suitable for applications in flash-based FPGAs
TL;DR: In this paper, an investigation of double channel (DC) AlGaN/GaN HEMT has been presented using extensive TCAD simulation under the influence of Single Event Transient (SET) effect.
Abstract: In this paper, investigation of Double Channel (DC) AlGaN/GaN HEMT has been presented using extensive TCAD simulation under the influence of Single Event Transient (SET) effect. Various models used to emulate Single Channel (SC) and DC HEMT in the TCAD are calibrated with the help of previously reported work. In order to present clear insight into the device behaviour, thermal model has also been included during device simulation. Presented results show that the generation of electron-hole pair due to heavy ion beam is significantly higher in DC HEMT during both OFF and ON state conditions. Ion beam having different Linear Energy Transfer (LET) and different position of Ion strike along with penetration depth has been used for investigating the SET effect on DC and SC AlGaN/GaN HEMT. The suitability of different metal gate work-function for heavy Ion detection has also been performed using both devices and DC HEMT (0.115 A/mm) demonstrated superior $\bigtriangleup \text{I} _{\mathrm{ DMAX}}$ as compared to SC HEMT (0.049 A/mm). The presence of a second channel in Double Channel (DC) HEMT leads to a device more sensitive towards the Single Event Transients (SET) Effect, thus, a more suitable candidate for radiation dosimeter as compared to Single Channel (SC) HEMT.
TL;DR: In this paper, the influence of annealing dwell time and temperature, as well as post-annealing thermal processing treatment on copper (Cu) protrusion in Cu through-glass vias (TGVs) were studied.
Abstract: In this work the influence of annealing dwell time and temperature, as well as post-annealing thermal processing treatment on copper (Cu) protrusion in Cu through-glass vias (TGVs) were studied. The Cu TGVs were made in Corning HPFS Fused Silica substrate, with a diameter and depth of $50~\mu \text{m}$ and $300~\mu \text{m}$ , respectively. For a constant annealing temperature of 400 °C, the results show a dependence of Cu protrusion with annealing dwell time, which saturates at about 240 min. Additional post-annealing thermal processing treatment, done at 400 °C (60 min dwell time) revealed that when an annealing dwell time ≥ 120 min is used no difference in the amount of Cu protrusion was found between the annealing step and the post-annealing thermal processing step. This indicates that downstream Cu protrusion can be eliminated when an annealing dwell time ≥ 120 min is used. On the other hand, from the temperature – dependent study of the annealing treatment, it was found that downstream Cu protrusion occurrence can be eliminated by performing annealing treatment at 450 °C (60 min dwell time), followed by post-annealing thermal processing treatment of 400 °C (60 min dwell time). Therefore, downstream Cu protrusion from a thermal processing treatment of 400 °C with 60 min dwell time can be eliminated either by using a longer annealing dwell time (120 min) at 400 °C or by increasing the annealing temperature to 450 °C, with a shorter dwell time of 60 min.
TL;DR: In this article, an experimental and numerical analysis of a buried P-pillar (BP) lateral double-diffused metal-oxide semiconductor (LDMOS) fabricated on a silicon-on-insulator (SOI) substrate is presented.
Abstract: This paper presents experimental and numerical analysis of a buried P-pillar (BP) lateral double-diffused metal-oxide semiconductor (LDMOS) fabricated on a silicon-on-insulator (SOI) substrate. The experimental results indicate that the specific on-resistance ( $R_{ {on,sp}}$ ) of the SOI BP-LDMOS is 9.5 $\text{m}\Omega \cdot {\mathrm{ cm}}^{{2}}$ with a breakdown voltage (BV) of 229 V, which corresponds to a figure of merit (FOM) of 5.52 MW/cm2. The analysis of structural parameter optimization of the SOI BP-LDMOS under different doping concentrations in the drift region and P-pillar layer is conducted via numerical simulation. The results show that the tested sample can achieve about 80% of the maximal FOM. Finally, the experimental and numerical investigation of the total ionizing dose (TID) radiation effect on the BV shift is performed. The TID tolerance of the measured SOI BP-LDMOS can reach 300 krad(Si) to support a voltage of 200 V. Due to the electric field modulation hardening design, compared with the conventional hardened SOI LDMOS, the studied hardened BP-LDMOS can achieve a significant improvement in the TID tolerance from 225 krad(Si) to 525 krad(Si).
TL;DR: This paper investigates system-level 3D TLC SSDs to characterize reliability and sub-health status based on field Self-Monitoring, Analysis and Reporting Technology (SMART) data, and predict impending failure proactively and derives some findings for each selected attribute in predetermined categories.
Abstract: 3D triple-level cell (TLC) NAND flash based solid state drive (SSD) is gradually becoming the dominant storage media in large-scale storage systems due to high storage density and low cost-per-bit. It ranks one of the top replaced hardware components in systems and their enormous amount also indirectly increases the failure probability, resulting in irreversible data loss disaster and service unavailability. This paper for the first time investigates system-level 3D TLC SSDs to characterize reliability and sub-health status based on field Self-Monitoring, Analysis and Reporting Technology (SMART) data, and predict impending failure proactively. We explore real-world datasets and derive some findings for each selected attribute in predetermined categories, contributing to the following feature selection and enhancing the interpretability of prediction models. Moreover, various machine learning models are trained to predict failures ahead of time, and experimental results show that random forest model can achieve 0.636 f 1-score and 0.662 MCC for a 7-day prediction horizon, and 42.5% true positive rate (TPR) with 0.00% false positive rate (FPR). Different time window sizes, training set fractions and ratios of negative to positive are analyzed as well.
TL;DR: In this paper, a gated-diode SCR-incorporated BJT (SIB) structure for ESD protection purpose is presented. But the SIB structure is not suitable for high voltage and high holding voltage and reduced trigger voltage.
Abstract: This work presents a novel gated- diode SCR-incorporated BJT (SIB) structure for ESD protection purpose. A gated diode built in the SIB structure modulates reverse-biased P+ / N-well diode for better junction breakdown control. This device could achieve high TLP second breakdown current /ESD threshold close to that of an SCR, very high holding voltage, and reduced trigger voltage, as well as excellent latchup immunity.
TL;DR: In this article, the authors analyzed the effect of single defects on the performance of MOS transistors and showed that the step heights are more likely bi-modal exponential distributed, i.e., the defects showing an enormous impact on the threshold voltage between nominally identical devices.
Abstract: To improve MOS transistors operating characteristics, such as the switching speed and power consumption, the dimensions of integrated devices are continuously decreased, amongst other advances. One of the main drawbacks of geometry scaling is the increased variability of the threshold voltage between nominally identical devices. The origin for this lies in defects located inside the oxide and at the interfacial layer between the oxide and the semiconductor. At the same time, the number of defects becomes a countable quantity in devices approaching the tens of nanometer scale. Furthermore, their impact on the device performance significantly increases, in a way that charge transitions from single defects can be observed directly from electrical measurements. To describe the degradation of the devices caused by single defects, one has to investigate the distribution of their impact on the $\mathbf {V_{\mathrm {th}}}$ shift. For SiON technologies, uni-modal exponential distributions of step heights of single defects have been reported in the literature. However, our results reveal that the step heights are more likely bi-modal exponential distributed. These findings are essential for the accurate evaluation of the tail of the distribution, i.e., the defects showing an enormous impact on $\mathbf {\Delta V_{\mathrm {th}}}$ . Such defects can give rise to an immediate failure of devices and circuits. In this study, the statistical distributions of the effect of single defects are created and analyzed. We compare the results to values calculated using the commonly applied charge sheet approximation (CSA) and show that the CSA significantly underestimates the real impact of the defects for the studied technology. Finally, we use the obtained distributions and analyze their effect on the variability of measure-stress-measure simulations using our compact physical modeling framework.
TL;DR: In this paper, the authors investigated the low-frequency noise of short channel triple-gate junctionless (TG JL) MOSFETs in the frequency and time domains before and after hot carrier aging (HCA).
Abstract: The low-frequency noise of short channel triple-gate junctionless (TG JL) MOSFET has been investigated in the frequency and time domains before and after hot carrier aging (HCA). The objective of this work is to investigate the interaction between HCA/flicker noise (1/f noise) and random telegraph noise (RTN) of short channel length device (L = 25 nm) exhibiting high density of interface traps. Significant variation in the noise spectral density has been observed between the fresh and the stressed device, related to the occurrence of generation-recombination (g-r) noise. Gate voltage dependence of g-r noise has been observed, assigned to gate dielectric traps and interface traps. In the fresh device, the noise is dominated by 1/f noise and multiple level RTN due to interface traps. In the stressed device, the 1/f noise is overlaid by multiple level RTN due to traps in the gate dielectric and at the gate insulator-silicon interface. The multiple level RTN relative amplitude can be described by the generic carrier number with correlated mobility fluctuations model as for the two level RTN detected in long channel devices (L = 65 and 95 nm).
TL;DR: In this article, the authors proposed two novel SET mitigation circuits with immune leaf nodes and demonstrated it through a few case studies, which improved SET hardness at control inputs of flip-flops by at least three times compared to unhardened inputs.
Abstract: In a spacecraft, flip-flops take part in holding operational configuration for long durations. Single event transients (SETs) at control inputs of such flip-flops can culminate in single event upsets (SEUs). An SEU may cause loss of one or more mission objectives or service disruption or life reduction of the spacecraft. Many radiation-hardened-by-design (RHBD) circuits are presented in the literature to improve the reliability of control inputs of flip-flops. However, leaf nodes of these circuits interfaced with control inputs remain vulnerable to SETs. This article proposes two novel SET mitigation circuits with immune leaf nodes and demonstrates it through a few case studies. The proposed circuits improve SET hardness at control inputs of flip-flops by at least three times compared to unhardened inputs. Comparison of important parameters with the published SET mitigation approaches shows that the proposed circuits require lesser transistors and consume low power.
TL;DR: By exploiting the resistance drift characteristics, drift compensation and drift-aware LDPC decoding schemes to improve reliability of PCM are proposed and simulation results show that the proposed schemes can significantly reduce the RBER and LDPC decode iterations.
Abstract: Phase-change memory (PCM) as emerging non-volatile memory has attracted more attention and considered as the promising replacement of the main memory. PCM has shown good scalability and high storage density, but data storage reliability has become a challenge and concern. When data are written into PCM cells by a phase transition between amorphous and crystalline, the resistance of each state drifts as the increase of storage time due to structural relaxation. As a result, raw bit error rates (RBER) become higher and higher, severely degrading the data storage reliability (i.e., an important problem in PCM). In this paper, we first find that high error percentage exists between the full amorphous and amorphous states in multilevel cell (MLC) PCM via a preliminary experiment, which is the main factor leading to high RBER. Then, we analyze why this phenomenon exists in PCM from the view of the resistance drift. Finally, by exploiting the resistance drift characteristics, we propose drift compensation and drift-aware LDPC decoding schemes to improve reliability of PCM. Simulation results show that the proposed schemes can significantly reduce the RBER and LDPC decoding iterations.
TL;DR: In this paper, an exponential dependence was found between Cu metallization thickness and the likelihood for the formation of circumferential cracks in a 400 °C annealed copper through-glass via (TGV) with a mean outer diameter of $47.5~\mu \text{m}$, made in Corning HPFS fused silica glass.
Abstract: This work aims at understanding and eliminating thermo-mechanically induced circumferential cracks that form during cooling for a 400 °C annealed copper (Cu) through-glass via (TGV) with a mean outer diameter of $47.5~\mu \text{m}$ , made in Corning HPFS fused silica glass. An exponential dependence was found between Cu metallization thickness and the likelihood for the formation of circumferential cracks. For the conditions used in this study, no cracks were formed in the HPFS fused silica substrate for Cu metallization thicknesses $ \mathbf { , however, for thicknesses $ \mathbf {\mathrm {\ge }}~12~\mu \text{m}$ , circumferential crack formation exponentially increased. From finite element analysis (FEA) studies, the corresponding threshold stresses for the initiation of circumferential stresses at $12~\mu \text{m}$ was predicted to be 140 MPa. Therefore, for 400 °C annealed Cu TGV with a mean outer diameter of $47.5~\mu \text{m}$ , made in HPFS fused silica substrate, circumferential stresses can be eliminated when Cu metallization thickness of less than $12~\mu \text{m}$ is used.
TL;DR: In this article, the authors presented a novel BTI resilient voltage bootstrapped Schmitt trigger (VB-ST) circuit with improved noise margin, leakage power and rail-to-rail voltage.
Abstract: This letter presents a novel BTI resilient voltage bootstrapped Schmitt trigger (VB-ST) circuit with improved noise margin, leakage power and rail-to-rail voltage. An only NMOS transistor is used in the proposed VB-ST circuit, which helps to reduce the aging effect specially Negative Bias Temperature Instability (NBTI) on the circuit. The reliability of the circuit is mainly analyzed by using the critical charge and soft error rate ratio (SERR), which indicates that the critical charge and SERR of the VB-ST circuit are improved by $6.31\times $ and reduced by 84.0%, respectively as compared to the CMOS circuit at 0.4V supply voltage. For the reliable and robust proposed circuit design, the quality factor (QF) is used as a performance metric and observed that the proposed circuit has $144\times $ improved QF as compared to the CMOS circuit.
TL;DR: In this paper, a side contact lateral Doping Field Effect Diode (SLFED) was proposed to overcome the short channel effects of a regular field effect diode (FED).
Abstract: This paper proposes a new structure named a Side Contact lateral Doping Field Effect Diode (SLFED) to overcome the short channel effects of a regular field effect diode (FED). The fabrication of this new structure is simple that can be fabricated by the standard CMOS process technology, and it offers good electrical characteristics. Furthermore, a comprehensive analysis of FEDs has presented. Our results show that the calculated Ion/Ioff ratio is several orders of magnitude larger than of the regular FED. For simulating the structures, we have applied semiconductor device simulation tools.
TL;DR: Application of Monte Carlo (MC) simulations in the statistical analysis of LED lumen maintenance is presented and the results are compared with the conventional and well-known TM-21 approach.
Abstract: Application of Monte Carlo (MC) simulations in the statistical analysis of LED lumen maintenance is presented in this paper. Lumen maintenance data is acquired using experimental tests accomplished in the electro-optics laboratory of the Mazinoor lighting industry, which is an accredited laboratory by Iranian National Standards organization. The sampling rate and the duration of the experiments are consistent with LM-80-15 standard introduced by the Illumination Engineering Society of North America. In some cases, due to the existence of nonlinear dynamics in real trends of light flux, particularly in the first 1,000 hours, features are not completely captured using traditional reliability assessment techniques such as TM-21. In this study, a two-phase model is applied to cover features in lumen maintenance data. Furthermore, to estimate the parameters of the dedicated model in mild and severe operating conditions, a nonlinear Kalman filter-based method known as the iterated extended Kalman filter (IEKF) is used. A set of MC simulations are run to construct the probability density functions (PDFs) for the estimated parameters. Each simulation uses different values of the parameters chosen from the corresponding distribution. Finally, lifetime PDFs are constructed to extract reliability indices. All of the simulations are conducted in MATLAB and the results are compared with the conventional and well-known TM-21 approach.