Showing papers in "IEEE Transactions on Device and Materials Reliability in 2012"

MEMS Reliability Review

Abstract: Microelectromechanical systems (MEMS) represents a technology that integrates miniaturized mechanical and electromechanical components (i.e., sensors and actuators) that are made using microfabrication techniques. MEMS devices have become an essential component in a wide range of applications, ranging from medical and military to consumer electronics. As MEMS technology is implemented in a growing range of areas, the reliability of MEMS devices is a concern. Understanding the failure mechanisms is a prerequisite for quantifying and improving the reliability of MEMS devices. This paper reviews the common failure mechanisms in MEMS, including mechanical fracture, fatigue, creep, stiction, wear, electrical short and open, contamination, their effects on devices' performance, inspection techniques, and approaches to mitigate those failures through structure optimization and material selection.

Lifetime Estimation of High-Power White LED Using Degradation-Data-Driven Method

Abstract: High-power white light-emitting diodes (HPWLEDs) have attracted much attention in the lighting market. However, as one of the highly reliable electronic products which may be not likely to fail under the traditional life test or even accelerated life test, HPWLED's lifetime is difficult to estimate by using traditional reliability assessment techniques. In this paper, the degradation-data-driven method (DDDM), which is based on the general degradation path model, was used to predict the reliability of HPWLED through analyzing the lumen maintenance data collected from the IES LM-80-08 lumen maintenance test standard. The final predicted results showed that much more reliability information (e.g., mean time to failure, confidence interval, reliability function, and so on) and more accurate prediction results could be obtained by DDDM including the approximation method, the analytical method, and the two-stage method compared to the IES TM-21-11 lumen lifetime estimation method. Among all these three methods, the two-stage method produced the highest prediction accuracy.

Effect of Thermal Stresses on Carrier Mobility and Keep-Out Zone Around Through-Silicon Vias for 3-D Integration

Abstract: Three-dimensional (3-D) integration with through-silicon vias (TSVs) has emerged as an effective solution to overcome the wiring limit imposed on device density and performance. However, thermal stresses induced in the TSV structures can affect the device performance by degrading carrier mobility and raise serious reliability concerns. In this paper, the effect of thermal stresses in TSV structures on carrier mobility and keep-out zone (KOZ) was investigated by focusing on the characteristics of the stresses near the surface where the electronic devices are located. The near-surface stresses were characterized by finite element analysis, and the stress effect on carrier mobility was evaluated by considering the piezoresistivity effect near the Si surface. In this paper, the elastic anisotropy of Si was taken into account to evaluate the effect on carrier mobility for both n- and p-channel MOSFET devices aligned along the [100] and [110] directions. The results showed a significant stress effect on carrier mobility, particularly for n-type Si with [100] device alignment and p-type Si with [110] device alignment. Based on these results, the dimension of the KOZ was estimated based on a criterion of 5% change in the carrier mobility. Finally, the effects due to stress interactions in a TSV array and plasticity in Cu vias on the KOZ were investigated. The effect of stress interaction was found to depend on the ratio of the pitch to diameter of the TSV array. When this ratio is less than 5, the stress interaction can increase the size of the KOZ. In contrast, the via material plasticity was found to be useful in reducing the stress level and hence the size of the KOZ.

Analysis and Design of Nanoscale CMOS Storage Elements for Single-Event Hardening With Multiple-Node Upset

Abstract: The occurrence of a single event with a multiple-node upset is likely to increase significantly in nanoscale CMOS due to reduced device size and power supply voltage scaling. This paper presents a comprehensive treatment (model, analysis, and design) for hardening storage elements (memories and latches) against a soft error resulting in a multiple-node upset at 32-nm feature size in CMOS. A novel 13T memory cell configuration is proposed, analyzed, and simulated to show a better tolerance to the likely multiple-node upset. The proposed hardened memory cell utilizes a Schmitt trigger (ST) design. As evidenced in past technical literature and used in this work, simulation of all node pairs by current sources results in an assessment similar to 3-D device tools; the simulation results show that the proposed 13T improves substantially over DICE in the likely and realistic scenarios of very diffused or limited charge sharing/collection. Moreover, the 13T cell achieves a 33% reduction in write delay and only a 5% (9%) increase in power consumption (layout area) compared to the DICE cell (consisting of 12 transistors). The analysis is also extended to hardened latches; it is shown that the latch with the highest critical charge has also the best tolerance to a multiple-node upset. Among the hardened latches, the ST designs have the best tolerance, and in particular, the transmission gate configuration is shown to be the most effective. Simulation results are provided using the predictive technology file for 32-nm feature size in CMOS. Monte Carlo simulation confirms the excellent multiple-node upset tolerance of the proposed hardened storage elements in the presence of process, voltage, and temperature variations in their designs.

Critical Concerns in Soldering Reactions Arising from Space Confinement in 3-D IC Packages

Abstract: Six critical issues relating to interfacial reactions arising from space confinement in 3-D integrated-circuit (3-D IC) packaging are presented in this paper. The first issue arises from the concern that intermetallics (IMCs) may occupy a large portion of the solder joint volume. It will be demonstrated that this concern is real even for Ni under bump metallurgy (UBM) or surface finish, which reacts very slowly with solders. The second issue relates to impingement and ripening of IMC grains. When IMCs occupy a large portion of a joint, the IMC grains growing from the opposite sides of a joint will eventually touch each other. The morphology evolution from this point on determines the final microstructure of a joint. Structural defects might form as a result of the impingement and ripening of IMC grains. The third issue is the rise of impurity concentration due to solder consumption. Many of the impurities in solders, such as those from electroplating, are not soluble in IMCs. As Sn reacts to form IMCs, these impurities are rejected from IMCs into the remaining solder. Consequently, the concentrations of these impurities increase with the progress of reaction. Eventually, these impurities are trapped between IMCs growing from the opposite directions. The impact of these trapped impurities on the properties of solder joints is an important issue. The fourth issue is similar to the third except that the role of impurities is replaced by inert alloy elements of solders. The most obvious element is Ag. The fifth issue arises from the fact that, as the size of a joint becomes smaller, the surface-area-to-volume ratio increases. This makes the impact of thin-film layers on UBM and surface finish become ever higher. One well-known element is Au. The so-called Au embrittlement issue may become relevant again. The last issue is the volume shrinkage from chemical reactions. Internal stress or structure defects may form because of this shrinkage. Experimental evidence will be used in this paper to illustrate these six issues, and the implications of these issues will be discussed.

A Review on the ESD Robustness of Drain-Extended MOS Devices

Abstract: This paper reviews electrostatic discharge (ESD) investigations on laterally diffused MOS (LDMOS) and drain-extended MOS (DeMOS) devices. The limits of the safe operating area of LDMOS/DeMOS devices and device physics under ESD stress are discussed under various biasing conditions and layout schemes. Specifically, the root cause of early filament formation is highlighted. Differences in filamentary nature among various LDMOS/DeMOS devices are shown. Based on the physical understanding, device optimization guidelines are given. Finally, an outlook on technology scaling is presented.

Transient Thermal Performance of IGBT Power Modules Attached by Low-Temperature Sintered Nanosilver

Abstract: Recently, to accurately study the transient thermal behavior of power modules, a transient thermal measurement system was developed to investigate the transient thermal behavior of insulated-gate bipolar transistor (IGBT) modules attached by nanosilver paste and two kinds of lead-free solders. We found that the transient thermal impedance of IGBT modules attached by nanosilver paste was 9% lower than that of the modules using SAC305 and SN100C with 40-ms heating pulse. In addition, finite-element analysis is employed to simulate thermal performance of the IGBT devices. The simulation shows that the transient thermal impedance of IGBT modules attached by nanosilver paste was also lower than that of the modules using lead-free solders. A convenient way was introduced to well predict the transient thermal behavior of IGBT power module. The calculated results agreed well with the measured one. The interface thermal impedance of sintered nanosilver and SNC100C are calculated to be 0.011 ~ 0.031 K/W and 0.022 ~ 0.042 K/W, respectively.

Through Silicon Via Reliability

Abstract: Vertical integration of diverse semiconductor technologies can be achieved by utilizing interconnections through entire silicon substrates, known as through silicon vias (TSVs). TSVs present an interesting case study for reliability evaluation, given the particular fabrication technologies, geometries, and potential failure modes associated with such structures. A specific TSV technology is introduced, and key parameters for reliability assessment, such as residual stress, resistance, leakage, and dielectric breakdown, are discussed. Reliability data are presented, including the characterization of TSV parameters as a function of various accelerated lifetime stress tests, as well as assessments of the density and impact of TSV manufacturing defects. The presented data demonstrate that while the TSV is inherently quite robust, latent manufacturing defects pose a significant risk to long-term reliability. Screening methodologies, defect modes, failure analysis methods, process improvement, and correspondingly improved defect density results are discussed. The results are considered pertinent to the development and reliability of novel 3-D integrated process technologies.

Diode-Triggered Silicon-Controlled Rectifier With Reduced Voltage Overshoot for CDM ESD Protection

Abstract: Diode-triggered silicon-controlled rectifiers (DTSCRs) are used for on-chip electrostatic discharge protection. The role of the trigger diode string in determining the transient voltage overshoot is investigated using a very fast transmission line pulse. A DTSCR containing only poly-bound trigger diodes has a voltage overshoot of just 1.5 V at 7 A, which is significantly less than what is found with STI-bound diodes. A DTSCR with only STI-bound trigger diodes has a lower leakage current. Therefore, DTSCRs with different trigger diode configurations may be suitable for different applications, e.g., high speed or low power.

Simulation Study of the Layout Technique for P-hit Single-Event Transient Mitigation via the Source Isolation

Abstract: In this paper, a layout technique for P-hit single-event transient (SET) mitigation via source isolation is studied by way of technology-computer-aided-design numerical simulations. The source-isolation layout design methodology is thoroughly discussed for the combinational standard cell. Based on a 90-nm twin-well CMOS technology, the simulation results indicate that the proposed “radiation hardened by design” (RHBD) technique can significantly reduce SET pulsewidth. The effects of the ion strike angles and strike locations on this hardened technique are also studied, and the area penalty is also discussed. When we combine the layout technique that utilizes the quenching effect with the proposed source-isolation layout technique, the RHBD standard-cell library can be further exploited for additional P-hit SET mitigation in the spaceborne integrated-circuit design.

Enhanced Detection of Double and Triple Adjacent Errors in Hamming Codes Through Selective Bit Placement

Abstract: Hamming codes that can correct one error per word are widely used to protect memories or registers from soft errors. As technology scales, radiation particles that create soft errors are more likely to affect more than 1 b when they impact a memory or electronic circuit. This effect is known as a multiple cell upset (MCU), and the registers or memory cells affected by an MCU are physically close. To avoid an MCU from causing more than one error in a given word, interleaving is commonly used in memories. With interleaving, cells that belong to the same logical word are placed apart such that an MCU affects multiple bits but on different words. However, interleaving increases the complexity of the memory device and is not suitable for small memories or content-addressable memories. When interleaving is not used, MCUs can cause multiple errors in a word that may not even be detected by a Hamming code. In this paper, a technique to increase the probability of detecting double and triple adjacent errors when Hamming codes are used is presented. The enhanced detection is achieved by placing the bits of the word such that adjacent errors result in a syndrome that does not match that of any single error. Double and triple adjacent errors are precisely the types of errors that an MCU would likely cause, and therefore, the proposed scheme will be useful to provide error detection for MCUs in memory designs.

Assessment of the Impact of Cosmic-Ray-Induced Neutrons on Hardware in the Roadrunner Supercomputer

Abstract: Microprocessor-based systems are a common design for high-performance computing (HPC) platforms. In these systems, several thousands of microprocessors can participate in a single calculation that may take weeks or months to complete. When used in this manner, a fault in any of the microprocessors could cause the computation to crash or cause silent data corruption (SDC), i.e., computationally incorrect results that originate from an undetected fault. In recent years, neutron-induced effects in HPC hardware have been observed, and researchers have started to study how neutrons impact microprocessor-based computations. This paper presents results from an accelerated neutron-beam test focusing on two microprocessors used in Roadrunner, which is the first petaflop supercomputer. Research questions of interest include whether the application running affects neutron susceptibility and whether different replicates of the hardware under test have different susceptibilities to neutrons. Estimated failures in time for crashes and for SDC are presented for the hardware under test, for the Triblade servers used for computation in Roadrunner, and for Roadrunner.

Three-Dimensional Wafer Stacking Using Cu–Cu Bonding for Simultaneous Formation of Electrical, Mechanical, and Hermetic Bonds

Abstract: Wafer-on-wafer stacking is demonstrated successfully using bumpless Cu-Cu bonding for the simultaneous formation of electrical connection, mechanical support, and hermetic frame for 3-D IC application. The ohmic behavior of the Cu-Cu bond is verified. A daisy chain of at least 44 000 contacts at a 15-μm pitch is connected successfully and sustains thermal cycling. Postbonding delamination is found to be strongly affected by the wafer curvature and bond strength. The Cu-Cu hermetic seal ring shows a helium leak rate more than ten times lower than the reject limit (5 × 10-8 atm · cm/s based on MIL-STD-883E standard) without underfill. This provides a robust IC-to-IC connection density of 4.4 × 105 cm-2, suitable for future wafer-level 3-D integration.

Chip–Package Interaction and Reliability Improvement by Structure Optimization for Ultralow- $k$ Interconnects in Flip-Chip Packages

Abstract: Mechanical failures in low-k interlayer dielectrics and related interfaces during flip-chip-packaging processes have raised serious reliability concerns. The problem can be traced to interfacial fracture induced by chip-package interaction (CPI). During the packaging processes, thermal stresses arise from the mismatch in coefficient of thermal expansion between the chip and the substrate, which can be directly coupled into the Cu/low-k interconnect structure to drive interfacial delamination. In this paper, finite-element method is used to evaluate the crack driving force induced by CPI and to examine its impact on the reliability of Cu/low-k interconnects for 45-nm technology and beyond. First, the characteristics of CPI are investigated for flip-chip packages using a 3-D multilevel global-to-local modeling method where the crack driving force for the interfacial delamination in Cu/low-k interconnect structures is evaluated. The effects of dielectric and packaging materials are examined for different low-k dielectrics and Pb-based and Pb-free solders. This study is then extended to explore the potential of using structural optimizations to improve the CPI reliability as the technology continues with dimensional scaling and implementation of porous ultralow- k materials.

Bias-Temperature Instabilities in 4H-SiC Metal–Oxide–Semiconductor Capacitors

Abstract: Bias-temperature instabilities (BTIs) are investigated for n- and p-substrate 4H-SiC metal-oxide-semiconductor (MOS) capacitors. The midgap voltage (Vmg) shifts positively under positive bias stress at high temperatures for n-substrate capacitors with 67.5-nm nitrided oxides and shifts negatively under negative bias for p-substrate capacitors with 55-nm nitrided oxides. The magnitudes of the Vmg shifts are less than 0.5 V for electric fields of magnitudes of approximately ± 3.1 MV/cm for up to one day of stress at 150°C or 20 min of stress at 300°C. Switched-bias stressing at 150°C causes partially reversible shifts for the n-substrate capacitors, while the p-substrate capacitors show monotonically increasing negative shifts. Based on the measured temperature dependence of the Vmg shifts, the effective activation energy for BTI that is measured between room temperature and 250°C is 0.12 ± 0.02 eV for the n-substrate capacitors (positive shifts) and 0.23 ± 0.02 eV for the p-substrate capacitors (negative shifts). The midgap voltage shifts in these wide-bandgap devices are caused by charge capture at deep interface traps and N-related defects at or near the SiC-SiO2 interface, which can be enhanced at elevated temperatures by the generation of additional carriers due to the ionization of deep dopants in the SiC during bias-temperature stress.

A (64,45) Triple Error Correction Code for Memory Applications

Abstract: Memories are commonly protected with error correction codes to avoid data corruption when a soft error occurs. Traditionally, per-word single error correction (SEC) codes are used. This is because they are simple to implement and provide low latency. More advanced codes have been considered, but their main drawback is the complexity of the decoders and the added latency. Recently, the use of one-step majority logic decodable codes has been proposed for memory protection. One-step majority logic decoding enables the use of low-complexity decoders, and low latency can also be achieved with moderate complexity. The main issue is that there are only a few codes that are one-step majority logic decodable. This restricts the choice of word lengths and error correction capabilities. In this paper, a method to derive new codes from a class of one-step majority logic decodable codes known as difference-set codes is proposed. The derived codes can also be efficiently implemented. As an example, a (64,45) triple error correction (TEC) code is derived and compared with existing SEC and TEC codes. The results presented enable a wider choice of word lengths and error correction capabilities that will be useful for memory designs.

Effects of Bonding Parameters on the Reliability of Fine-Pitch Cu/Ni/SnAg Micro-Bump Chip-to-Chip Interconnection for Three-Dimensional Chip Stacking

Abstract: As the demands for portable electronic products increase, through-silicon-via (TSV)-based three-dimensional integrated-circuit (3-D IC) integration is becoming increasingly important. Micro-bump-bonded interconnection is one approach that has great potential to meet this requirement. In this paper, a 30-μm pitch chip-to-chip (C2C) interconnection with Cu/Ni/SnAg micro bumps was assembled using the gap-controllable thermal bonding method. The bonding parameters were evaluated by considering the variation in the contact resistance after bonding. The effects of the bonding time and temperature on the IMC thickness of the fabricated C2C interconnects are also investigated to determine the correlation between its thickness and reliability performance. The reliability of the C2C interconnects with the selected underfill was studied by performing a -55°C- 125°C temperature cycling test (TCT) for 2000 cycles and a 150°C high-temperature storage (HTS) test for 2000 h. The interfaces of the failed samples in the TCT and HTS tests are then inspected by scanning electron microscopy (SEM), which is utilized to obtain cross-sectional images. To validate the experimental results, finite-element (FE) analysis is also conducted to elucidate the interconnect reliability of the C2C interconnection. Results show that consistent bonding quality and stable contact resistance of the fine-pitch C2C interconnection with the micro bumps were achieved by giving the appropriate choice of the bonding parameters, and those bonded joints can thus serve as reliable interconnects for use in 3-D chip stacking.

Rapid Light Output Degradation of GaN-Based Packaged LED in the Early Stage of Humidity Test

Abstract: An initial sharp decrease in the light output of a high-power light-emitting diode is observed when it is exposed to humid condition. TGA and energy-dispersive system analyses confirm the possibility of moisture entrapment in the silicone encapsulation; moreover, the light scattering model verifies qualitatively the scattering of the light due to the entrapped moisture, and it is this scattering that renders an initial sharp drop in the light output. The finding shows the importance of pore size of the silicone gel in order to prevent such sharp decrease in the light output under a humid environment.

Reliability Assessment of Through-Silicon Vias in Multi-Die Stack Packages

Abstract: A thermo-mechanical reliability study of through-silicon vias (TSVs) is presented in this paper. TSVs are used to interconnect stacked dies to achieve 3-D packages. As the core of the TSV contains high coefficient of thermal expansion (CTE) copper surrounded by low-CTE SiO2 and Si materials, the thermo-mechanical reliability of TSVs is a concern. When dies with such TSVs are stacked and packaged, the presence of additional structures and associated materials could introduce different thermo-mechanical concerns compared with free-standing wafers. This paper presents 3-D finite-element models for studying the thermo-mechanical stresses in TSVs in free-standing wafers and in stacked dies, which are packaged. Warpage measurements have been used to validate the finite-element modeling approach. The results from the finite-element models show that the TSV stresses in a packaging configuration are typically lower than the TSV stresses in a free-standing wafer configuration. In addition, it is seen that the microbumps connecting adjacent dies experience high magnitude of inelastic strain, indicating that such locations are of reliability concern.

An SCR-Incorporated BJT Device for Robust ESD Protection With High Latchup Immunity in High-Voltage Technology

Abstract: A silicon-controlled rectifier (SCR)-incorporated BJT with high holding voltage is developed for electrostatic discharge (ESD) protection in a 0.6 μm high-voltage 10 V process. This device consists simply of a floating P+ diffusion incorporated in a parasitic NPN BJT. A robust 6-7 kV ESD threshold and high-latchup-immune holding voltage of 15-18 V can be achieved by layout optimization of the NPN-N+ -collector to floating P+ -diffusion spacing and the floating P+ diffusion width. It can be equivalently regarded as parallel connection of an incorporated PNPN SCR part and an NPN BJT part. The incorporated SCR part is further composed of a parasitic SCR in series with a reverse-biased PN diode formed by the floating P+ region and N-well. The further analysis shows that the floating P+ diffusion is the key part of this SCR-incorporated BJT. The parasitic reverse-biased PN diode sustains most of the high holding voltage. The parasitic NPN BJT plays a major role in ESD current conduction, while the incorporated SCR in series with the reverse-biased PN diode is the secondary conduction path.

Simulations of Damage, Crack Initiation, and Propagation in Interlayer Dielectric Structures: Understanding Assembly-Induced Fracture in Dies

Abstract: Performance enhancement by lowering the dielectric constant of interlayer dielectric (ILD) materials often compromises the mechanical integrity of the dielectric stack. At the present time, fracture in the ILD stacks induced by assembly to either an organic substrate or a die stack (3-D) is an important reliability consideration. These interactions include what is popularly referred to as the chip-package interactions. In this paper, we develop insights on the potential crack initiation site within the ILD, die-substrate geometrical parameters that cause most damage, as well as insights on the manufacturing process that is critical to failure. Towards this end, we utilize analytical models based on classical elasticity theory as well as sophisticated numerical techniques that are capable of nucleating and propagating cracks at arbitrary locations within the structure without remeshing. Specifically, we analytically estimate the strength of singularities at all the possible multimaterial corners in the ILD stack to provide insight on the likely damage nucleation sites for various material configurations in the ILD stack. Two novel numerical approaches are used for fracture simulation. In the first, cracks are modeled as discontinuous enrichments over an underlying continuous behavioral approximation. In the second approach, the underlying material description is enriched with a cohesive damage description whose stiffness is evolved according to a prescribed damage law. Multilevel finite-element models are used to determine the load imposed on the ILD structure by the substrate. Maximum damage induced in the ILD stack by the above load is used as an indicator of the reliability risk. Parametric simulations are conducted by varying ILD material, die size, die thickness, as well as the solder material. Through analytical models of bonded assemblies, we identify groups of relevant dimensionless parameters to relate the numerically estimated damage in ILD stacks to the die/substrate material and geometrical parameters. We demonstrate that the damage in the ILD stack is least when the flexural rigidity of the die is matched to that of the assembled substrate. We also demonstrate that ILD damage is only weakly correlated to shear deformation on the die surface due to assembly. We generalize the above observations into mathematical fits (for use as design rules) relating damage in ILD stacks to ILD material choice, relative substrate flexural rigidity, and die size.

Moisture-Induced Surface Corrosion in AZO Thin Films Formed by Atomic Layer Deposition

Abstract: Aluminum-doped zinc oxide (AZO) thin film is a viable alternative to tin-doped indium oxide, the dominant transparent conducting oxide used in solar cells. The durability of the AZO thin films grown by atomic layer deposition technique, which is known to form layers with atomic layer precision, is studied. The AZO films were subjected to the harsh environmental conditions of varying temperatures and humidity, and their changes in surface morphology and conductivity are investigated. Four different combinations of temperature (100°C and 20°C) and relative humidity (100% and 20%) were used. It was found that the films exposed to the high-moisture and temperature conditions resulted in surface corrosion and lowered conductivity. However, SEM cross-sectional images showed that the bulk of the film was unaffected. The corroded surface had contaminants deposited from the measurement chamber as observed from XPS elemental analysis. Detailed phase analysis showed the presence of zinc hydroxide and zinc carbonate inside the corroded regions.

Technology Scaling Effect on the Relative Impact of NBTI and Process Variation on the Reliability of Digital Circuits

Abstract: The impact of negative bias temperature instability (NBTI) on circuit reliability is typically assessed without accounting for the variability associated with the manufacturing process. With technology progression, manufacturing process variability scales more aggressively than transistor NBTI lifetime. Hence, a clear link between transistor and circuit reliability that takes variability into account is imperative to analyze circuit reliability. We propose a figure of merit termed fall-out to describe the proportion of circuits whose frequencies would exceed the initial manufacturing distribution. We use fall-out to assess NBTI and process variability in tandem, and we show that the fall-out of circuit frequency (or timing delay) peaks and diminishes as technology scales. We propose that the fall-out of a ring oscillator can be used as a worst-case indicator of circuit reliability in any given technology.

Characterization of SOA in Time Domain and the Improvement Techniques for Using in High-Voltage Integrated Circuits

Abstract: Safe operating area (SOA) in power semiconductors is one of the most important factors affecting device reliability. The SOA region of power MOSFETs must be well characterized for using in circuit design to meet the specification of applications, particularly including the time domain of circuit operations. In this paper, the characterization of SOA in the time domain is performed with the experimental measurement on silicon devices, and the useful techniques to improve SOA of power MOSFETs for using in high-voltage integrated circuits are overviewed.

Neutron-Induced Upsets in NAND Floating Gate Memories

Abstract: We investigate atmospheric neutron effects on floating-gate cells in NAND Flash memory devices. Charge loss is shown to occur, particularly at the highest program levels, causing raw bit errors in multilevel cell NAND, but to an extent that does not challenge current mandatory error correction specifications. We discuss the physical mechanisms and analyze scaling trends, which show a rapid increase in sensitivity for decreasing feature size.

Investigation of Modeling System ESD Failure and Probability Using IBIS ESD Models

Abstract: Due to growing number of embedded electronics, estimating failure related to system-level electrostatic discharge (ESD) consideration has become a major concern. In this paper, a behavioral modeling methodology to predict ESD failures at system level is proposed and validated. The proposed models enable time-domain simulation to determine the voltage and current waveforms inside and outside an integrated circuit during ESD events and then to predict the susceptibility of an electronic system to ESD. The purpose of this methodology is based on the improvement of Input/output Buffer Information Specification files widely used in signal integrity simulation. A simple case study is proposed to investigate the susceptibility of latch devices to transient stresses. Simulations and measurements are compared. Analytical formulations to determine the probability of susceptibility failure are proposed and compared with measurements.

HBM ESD Robustness of GaN-on-Si Schottky Diodes

Abstract: The ESD robustness of GaN-on-Si Schottky diodes is investigated using on-wafer HBM and TLP. Both forward and reverse diode operation modes are analyzed as a function of device geometry, which strongly impact the corresponding failure mechanism. In forward mode, the anode-to-cathode length reduction and the total device width increase are beneficial for ESD robustness; however, in reverse mode, the ESD robustness does not depend on the total device width and saturates at around 400 V for medium and long anode-to-cathode lengths. The corresponding failure mechanisms are respectively attributed to the current distribution and Si substrate breakdown under forward and reverse mode ESD stresses.

Physics-Based Models for EM and SM Simulation in Three-Dimensional IC Structures

Abstract: Relaxation of stress generated inside through-silicon via (TSV), in regions of interconnect and regions of silicon adjusted to TSV by microstructure evolution during high-temperature anneal and by wafer/die cooling down to test/operation conditions, is critical for establishing a final equilibrium state. A model for stress relaxation governed by vacancy generation and migration is developed. The comparative study of the steady-state distributions of stress and concentrations of vacancies and plated atoms in via-last and via-middle TSVs allows us to conclude that different types of TSVs are characterized by miniscule differences in the level of generated stress. It is found that the grain size distribution along the TSV height can affect the level of generated stress. TSVs with the largest grains, located in the TSV center, and the smaller ones, located in the TSV top and bottom, seem to generate a smaller outside stress compared to other simulated grain size distributions. It is shown that additional stress gradients in interconnect segments, generated by nearby TSVs, can be relaxed at the proper planed anneal step. The performed simulation analysis allows us to conclude that the introduction of TSVs as a new element in 3-D IC stacking technology does not introduce any significant changes in the EM-related reliability.

Lead-Free Solder Joint Void Evolution During Multiple Subsequent High-Temperature Reflows

Abstract: Entrapment of volatiles during lead-free solder joint formation results in the creation of voids which may have a negative impact on the joint's mechanical and/or electrical performances. According to IPC-J-STD-001E and IPC-A-610E specifications, the post-surface-mount-technology cumulative voiding criterion in lead-free solder joints is less than 25% for a second-level interconnect. For solder joints that experience multiple high-temperature reflow processes after completion of assembly, however, it is important to understand and predict how these voids will interact and evolve during subsequent high-temperature exposures. In this paper, both in situ 2-D X-ray imaging and 3-D X-ray tomography were used to study the growth kinetics of solder joint voids during multiple reflow cycles. The results demonstrate that voids grow and move during each reflow cycle. The growth kinetics has been shown to follow a diffusion-controlled mechanism based on a model for out-gassing bubble growth in a supersaturated molten solder liquid.

Position-Dependent Nanoscale Breakdown Characteristics of Thin Silicon Dioxide Film Subjected to Mechanical Strain

Abstract: This paper investigates the nanoscale breakdown characteristics of thin silicon dioxide (SiO2) films subjected to mechanical strain. A uniaxial compressive strain or a tensile strain was applied to the oxide samples using a homemade bending tool followed by the application of a ramped voltage stress (RVS) or a constant voltage stress to the oxide samples by means of a conductive atomic force microscope tip. The nanoscale current versus voltage (I-V) characteristics and the cumulative failure distributions of the oxide breakdown voltage for the RVS as well as the nanoscale current versus time (I-t) characteristics and cumulative failure distributions of time to breakdown at various surface positions along the strain axis were determined. The nanoscale breakdown characteristics of the strained oxide samples after Co-60 γ-ray irradiation were also investigated. It was found that the central region of both the preand postirradiated strained samples always exhibited a higher oxide leakage current, a lower oxide breakdown voltage, and a shorter time to breakdown than the side regions, regardless if they were under compressive or tensile strain. Our experimental results also showed that interfacial strain release as well as the nanoscale bias-annealing effect increased the Weibull slope β and 63%TBR in the center region of the postirradiated strained oxide samples, compared to the preirradiated ones.