Many materials systems are currently under consideration as potential replacements for SiO2 as the gate dielectric material for sub-0.1 μm complementary metal–oxide–semiconductor (CMOS) technology. A systematic consideration of the required properties of gate dielectrics indicates that the key guidelines for selecting an alternative gate dielectric are (a) permittivity, band gap, and band alignment to silicon, (b) thermodynamic stability, (c) film morphology, (d) interface quality, (e) compatibility with the current or expected materials to be used in processing for CMOS devices, (f) process compatibility, and (g) reliability. Many dielectrics appear favorable in some of these areas, but very few materials are promising with respect to all of these guidelines. A review of current work and literature in the area of alternate gate dielectrics is given. Based on reported results and fundamental considerations, the pseudobinary materials systems offer large flexibility and show the most promise toward success...

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High-κ gate dielectrics: Current status and materials properties considerations

Learn the basic properties and designs of modern VLSI devices, as well as the factors affecting performance, with this thoroughly updated second edition. The first edition has been widely adopted as a standard textbook in microelectronics in many major US universities and worldwide. The internationally-renowned authors highlight the intricate interdependencies and subtle tradeoffs between various practically important device parameters, and also provide an in-depth discussion of device scaling and scaling limits of CMOS and bipolar devices. Equations and parameters provided are checked continuously against the reality of silicon data, making the book equally useful in practical transistor design and in the classroom. Every chapter has been updated to include the latest developments, such as MOSFET scale length theory, high-field transport model, and SiGe-base bipolar devices.

/pdf/fundamentals-of-modern-vlsi-devices-471xd7l9pf.pdf

Fundamentals of Modern VLSI Devices

The compelling demand for higher performance and lower power consumption in electronic systems is the main driving force of the electronics industry's quest for devices and/or architectures based on new materials. Here, we provide a review of electronic devices based on two-dimensional materials, outlining their potential as a technological option beyond scaled complementary metal-oxide-semiconductor switches. We focus on the performance limits and advantages of these materials and associated technologies, when exploited for both digital and analog applications, focusing on the main figures of merit needed to meet industry requirements. We also discuss the use of two-dimensional materials as an enabling factor for flexible electronics and provide our perspectives on future developments.

Electronics based on two-dimensional materials

Power dissipation is a fundamental problem for nanoelectronic circuits. Scaling the supply voltage reduces the energy needed for switching, but the field-effect transistors (FETs) in today's integrated circuits require at least 60 mV of gate voltage to increase the current by one order of magnitude at room temperature. Tunnel FETs avoid this limit by using quantum-mechanical band-to-band tunnelling, rather than thermal injection, to inject charge carriers into the device channel. Tunnel FETs based on ultrathin semiconducting films or nanowires could achieve a 100-fold power reduction over complementary metal-oxide-semiconductor (CMOS) transistors, so integrating tunnel FETs with CMOS technology could improve low-power integrated circuits.

Tunnel field-effect transistors as energy-efficient electronic switches

Electron and ambipolar transport in organic field-effect transistors.

This paper presents a dual supply voltage strategy for reduction of the total (static and dynamic) power of high performance CMOS processors. By expressing CMOS delay, static power, and dynamic power in terms of the power supply voltage V/sub DD/ and threshold voltage V/sub T/, an optimization procedure that takes the circuit activity factor into account is performed to find the V/sub DD/ and V/sub T/ for minimum total power at given performance levels. It is shown that 50% power reduction or 20% performance enhancement can be attained by adopting both a low (0.5 V) supply voltage for high-activity circuits and a high (1.2 V) supply voltage for low-activity circuits in a 100 nm-node CMOS technology.

https://www.vlsisymposium.org/Past/02web/technology/tec_pdf/T11p1.pdf

Supply voltage strategies for minimizing the power of CMOS processors

We present a novel fully-depleted SOI CMOS technology with dielectrically-isolated polysilicon back gates, achieved by a double BOX substrate combined with dual-depth shallow trench isolation. CMOS devices down to 30nm gate length are fabricated with high-κ/metal gates. A novel isolation structure with liners is shown to achieve robust isolation between devices and back gates. Effective back gate control of CMOS V T is demonstrated, which enables dual-V T design with power gating capability. Suppression of leakage and performance tolerances due to systematic process variations is discussed.

FDSOI CMOS with dielectrically-isolated back gates and 30nm L G high-γ/metal gate

A high performance CMOS process using mix e-beam/optical lithography has been developed for VLSI applications. The 0.5 ?m channel devices are fabricated with shallow N+ and P+ source/drain junctions. Self-aligned silicide on gate and diffusions reduces the sheet resistance to 5 ohm/sq.. The shallow retrograde N-well formed by multiple high energy phosphorous implants without a drive-in a allows the use of thin P/P+ epi for latch-up control.

0.5 Micron Gate CMOS Technology Using E-Beam/Optical Mix Lithography

The n-channel insulated-gate field-effect transistor offers a factor of 2 to 3.4 mobility advantage (depending on crystal orientation and substrate doping level) over p-channel devices. In addition, several advantages result from the fact that the work function difference between an aluminum gate and the silicon substrate is about -0.8 volt for a p substrate compared with about zero for an n substrate. In particular, this results in a low threshold voltage that allows the use of a substrate bias to adjust the threshold voltage over a useful design range resulting in an added flexibility in choice of thresholds and substrate doping, a reduction in the effect of source-substrate bias on device threshold, decreased junction capacitance, and larger parasitic thick-oxide thresholds for a given insulator thickness. The speed, power, and density advantages of the n-channel device are illustrated for logic and memory circuits using representative n- and p-channel device designs.

IGFET circuit performance-n-channel versus p-channel

This embedded-DRAM macro is designed as a DRAM cache for a future gigahertz microprocessor system based on a logic-based DRAM technology. The most notable feature of this macro is its ability to run synchronously with a gigahertz CPU clock in a fully pipelined fashion. It is designed to operate with a 1-GHz clock signal at 85/spl deg/C, nominal process parameters, and a 10% degraded V/sub DD/. The design is fully pipelined and synchronous with 16 independent subarrays. With 1-kb wide I/0 and a 1-GHz clock, the maximum data rate becomes 1 Tb per second. The address access time is 3.7 ns, four cycles with a 1-GHz clock. The subarray cycle time is 12 ns.

R.H. Dennard

Papers

Supply voltage strategies for minimizing the power of CMOS processors

FDSOI CMOS with dielectrically-isolated back gates and 30nm L G high-γ/metal gate

0.5 Micron Gate CMOS Technology Using E-Beam/Optical Mix Lithography

IGFET circuit performance-n-channel versus p-channel

1-GHz fully pipelined 3.7-ns address access time 8 k/spl times/1024 embedded synchronous DRAM macro