Many materials systems are currently under consideration as potential replacements for SiO2 as the gate dielectric material for sub-0.1 μm complementary metal–oxide–semiconductor (CMOS) technology. A systematic consideration of the required properties of gate dielectrics indicates that the key guidelines for selecting an alternative gate dielectric are (a) permittivity, band gap, and band alignment to silicon, (b) thermodynamic stability, (c) film morphology, (d) interface quality, (e) compatibility with the current or expected materials to be used in processing for CMOS devices, (f) process compatibility, and (g) reliability. Many dielectrics appear favorable in some of these areas, but very few materials are promising with respect to all of these guidelines. A review of current work and literature in the area of alternate gate dielectrics is given. Based on reported results and fundamental considerations, the pseudobinary materials systems offer large flexibility and show the most promise toward success...

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High-κ gate dielectrics: Current status and materials properties considerations

Learn the basic properties and designs of modern VLSI devices, as well as the factors affecting performance, with this thoroughly updated second edition. The first edition has been widely adopted as a standard textbook in microelectronics in many major US universities and worldwide. The internationally-renowned authors highlight the intricate interdependencies and subtle tradeoffs between various practically important device parameters, and also provide an in-depth discussion of device scaling and scaling limits of CMOS and bipolar devices. Equations and parameters provided are checked continuously against the reality of silicon data, making the book equally useful in practical transistor design and in the classroom. Every chapter has been updated to include the latest developments, such as MOSFET scale length theory, high-field transport model, and SiGe-base bipolar devices.

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Fundamentals of Modern VLSI Devices

The compelling demand for higher performance and lower power consumption in electronic systems is the main driving force of the electronics industry's quest for devices and/or architectures based on new materials. Here, we provide a review of electronic devices based on two-dimensional materials, outlining their potential as a technological option beyond scaled complementary metal-oxide-semiconductor switches. We focus on the performance limits and advantages of these materials and associated technologies, when exploited for both digital and analog applications, focusing on the main figures of merit needed to meet industry requirements. We also discuss the use of two-dimensional materials as an enabling factor for flexible electronics and provide our perspectives on future developments.

Electronics based on two-dimensional materials

Power dissipation is a fundamental problem for nanoelectronic circuits. Scaling the supply voltage reduces the energy needed for switching, but the field-effect transistors (FETs) in today's integrated circuits require at least 60 mV of gate voltage to increase the current by one order of magnitude at room temperature. Tunnel FETs avoid this limit by using quantum-mechanical band-to-band tunnelling, rather than thermal injection, to inject charge carriers into the device channel. Tunnel FETs based on ultrathin semiconducting films or nanowires could achieve a 100-fold power reduction over complementary metal-oxide-semiconductor (CMOS) transistors, so integrating tunnel FETs with CMOS technology could improve low-power integrated circuits.

Tunnel field-effect transistors as energy-efficient electronic switches

Electron and ambipolar transport in organic field-effect transistors.

After decades of continuous scaling, further advancement of silicon microelectronics across the entire spectrum of computing applications is today limited by power dissipation. While the trade-off between power and performance is well-recognized, most recent studies focus on the extreme ends of this balance. By concentrating instead on an intermediate range, an ~ 8× improvement in power efficiency can be attained without system performance loss in parallelizable applications-those in which such efficiency is most critical. It is argued that power-efficient hardware is fundamentally limited by voltage scaling, which can be achieved only by blurring the boundaries between devices, circuits, and systems and cannot be realized by addressing any one area alone. By simultaneously considering all three perspectives, the major issues involved in improving power efficiency in light of performance and area constraints are identified. Solutions for the critical elements of a practical computing system are discussed, including the underlying logic device, associated cache memory, off-chip interconnect, and power delivery system. The IBM Blue Gene system is then presented as a case study to exemplify several proposed directions. Going forward, further power reduction may demand radical changes in device technologies and computer architecture; hence, a few such promising methods are briefly considered.

Practical Strategies for Power-Efficient Computing Technologies

Modeling and characterization of long on-chip interconnections for high-performance microprocessors

A 0.5-µm-channel CMOS design optimized for liquid-nitrogen temperature operation is described. Thin gate oxide (12.5 nm) and dual polysilicon work functions (n+-poly gate for n-channel and p+-poly for p-channel transistors) are used. The power supply voltage is chosen to be 2.5 V based on performance, hot-carrier effects, and power dissipation considerations. The doping profiles of the channel and the background (substrate or well) are chosen to optimize the mobility, substrate sensitivity, and junction capacitance with minimum process complexity. The reduced supply voltage enables the use of silicided shallow arsenic and boron junctions, without any intentional junction grading, to control short-channel effects and to reduce the parasitic series resistance at 77 K. The same self-aligned silicide over the polysilicon gate electrode reduces the sheet resistance (as low as 1 Ω/sq at 77 K) and provides the strapping between the gates of the complementary transistors. The design has been demonstrated by a simple n-well/p-substrate CMOS process with very good device characteristics and ring-oscillator performance at 77 K.

Submicrometer-channel CMOS for low-temperature operation

Micrometer-dimension n-channel silicon-gate MOSFET's optimized for high-performance logic applications have been designed and characterized for both room-temperature and liquid-nitrogen-temperature operation. Appropriate choices of design parameters are shown to give proper device thresholds which are reasonably independent of channel length and width. Depletion-type devices are characterized at room temperature for load device use. Logic performance capability is demonstrated by test results on NOR circuits for representative fan-out and loading conditions. Unloaded ring oscillators achieved switching delays down to 240 ps at room temperature and down to 100 ps at liquid nitrogen temperature.

1 &#181;m MOSFET VLSI technology: Part II&#8212;Device designs and characteristics for high-performance logic applications

An advanced 0.1 /spl mu/m CMOS technology on SOI is presented. In order to minimize short channel effects, relatively thick nondepleted (0.15 /spl mu/m) SOI film, highly nonuniform channel doping and source-drain extension-halo were used. Excellent short channel effects (SCE) down to channel lengths below 0.1 /spl mu/m were obtained. It is shown that undepleted SOI results in better short channel effect when compared to ultrathin depleted SOI. Devices with little short channel effect all the way to below 500 /spl Aring/ effective channel length were obtained. Furthermore, utilization of source-drain extension-halo minimizes the bipolar effect inherent in the floating body. These devices were applied to a variety of circuits: Very high speeds were obtained: Unloaded delay was 20 ps, unloaded NAND (FI=FO=3) was 64 ps, and loaded NAND (FI=FO=3, C/sub L/=0.3 pF) delay was 130 ps at supply of 1.8 V. This technology was applied to a self-resetting 512 K SRAM. Access times of 2.5 ns at 1.5 V and 3.5 ns at 1.0 V were obtained. >

R.H. Dennard

Papers

Practical Strategies for Power-Efficient Computing Technologies

Modeling and characterization of long on-chip interconnections for high-performance microprocessors

Submicrometer-channel CMOS for low-temperature operation

1 µm MOSFET VLSI technology: Part II—Device designs and characteristics for high-performance logic applications

A room temperature 0.1 /spl mu/m CMOS on SOI

R.H. Dennard

Papers

Practical Strategies for Power-Efficient Computing Technologies

Modeling and characterization of long on-chip interconnections for high-performance microprocessors

Submicrometer-channel CMOS for low-temperature operation

1 &#181;m MOSFET VLSI technology: Part II&#8212;Device designs and characteristics for high-performance logic applications

A room temperature 0.1 /spl mu/m CMOS on SOI

1 µm MOSFET VLSI technology: Part II—Device designs and characteristics for high-performance logic applications