Many materials systems are currently under consideration as potential replacements for SiO2 as the gate dielectric material for sub-0.1 μm complementary metal–oxide–semiconductor (CMOS) technology. A systematic consideration of the required properties of gate dielectrics indicates that the key guidelines for selecting an alternative gate dielectric are (a) permittivity, band gap, and band alignment to silicon, (b) thermodynamic stability, (c) film morphology, (d) interface quality, (e) compatibility with the current or expected materials to be used in processing for CMOS devices, (f) process compatibility, and (g) reliability. Many dielectrics appear favorable in some of these areas, but very few materials are promising with respect to all of these guidelines. A review of current work and literature in the area of alternate gate dielectrics is given. Based on reported results and fundamental considerations, the pseudobinary materials systems offer large flexibility and show the most promise toward success...

/pdf/high-k-gate-dielectrics-current-status-and-materials-zjvba0c4u8.pdf

High-κ gate dielectrics: Current status and materials properties considerations

Learn the basic properties and designs of modern VLSI devices, as well as the factors affecting performance, with this thoroughly updated second edition. The first edition has been widely adopted as a standard textbook in microelectronics in many major US universities and worldwide. The internationally-renowned authors highlight the intricate interdependencies and subtle tradeoffs between various practically important device parameters, and also provide an in-depth discussion of device scaling and scaling limits of CMOS and bipolar devices. Equations and parameters provided are checked continuously against the reality of silicon data, making the book equally useful in practical transistor design and in the classroom. Every chapter has been updated to include the latest developments, such as MOSFET scale length theory, high-field transport model, and SiGe-base bipolar devices.

/pdf/fundamentals-of-modern-vlsi-devices-471xd7l9pf.pdf

Fundamentals of Modern VLSI Devices

The compelling demand for higher performance and lower power consumption in electronic systems is the main driving force of the electronics industry's quest for devices and/or architectures based on new materials. Here, we provide a review of electronic devices based on two-dimensional materials, outlining their potential as a technological option beyond scaled complementary metal-oxide-semiconductor switches. We focus on the performance limits and advantages of these materials and associated technologies, when exploited for both digital and analog applications, focusing on the main figures of merit needed to meet industry requirements. We also discuss the use of two-dimensional materials as an enabling factor for flexible electronics and provide our perspectives on future developments.

Electronics based on two-dimensional materials

Power dissipation is a fundamental problem for nanoelectronic circuits. Scaling the supply voltage reduces the energy needed for switching, but the field-effect transistors (FETs) in today's integrated circuits require at least 60 mV of gate voltage to increase the current by one order of magnitude at room temperature. Tunnel FETs avoid this limit by using quantum-mechanical band-to-band tunnelling, rather than thermal injection, to inject charge carriers into the device channel. Tunnel FETs based on ultrathin semiconducting films or nanowires could achieve a 100-fold power reduction over complementary metal-oxide-semiconductor (CMOS) transistors, so integrating tunnel FETs with CMOS technology could improve low-power integrated circuits.

Tunnel field-effect transistors as energy-efficient electronic switches

Electron and ambipolar transport in organic field-effect transistors.

We show that with a forward body bias, CMOS performance can be improved for those applications which are primarily concerned with speed, and for those which have fixed performance targets but desire lower switching energy (higher MHz/mW). Thus V/sub t/ can be set according to standby power requirement or device design (well and halo engineering), forward body bias is then applied to improve speed or to reduce active power. No compromise in I/sub off/ results if the forward bias is applied when the circuits are active, during which time I/sub off/ and the leakage current are small compared to the switching current. Therefore a low-power CMOS strategy should use a MOSFET as a four-terminal device with a fast top gate and a slow bottom gate shared by a block. Deep-trench isolation with STI provides fine-grain isolation for body bias blocks without area penalty. Making the body available also improves the device analog properties and enables new applications. We present an active-well VCO/mixer as an example.

CMOS with active well bias for low-power and RF/analog applications

A six-mask 1-µm CMOS process with many self-aligned features is described. It uses a thin p-type epitaxial layer on a p+substrate and a retrograde n-well. Self-aligned TiSi 2 is formed on n+and p+diffusions to reduce the sheet resistance and to make butted source contacts. It is shown that n+poly-gated p-channel devices can be properly designed with low threshold magnitudes and good turn-off characteristics. With a 5-V supply, the minimum gate delay of unloaded CMOS ring oscillators is 150 ps/stage. Furthermore, it is demonstrated that this CMOS technology is latchup free since the holding voltage for latchup is higher than 5 V.

A self-aligned 1-&#181;m-channel CMOS technology with retrograde n-well and thin epitaxy

This paper reports an accurate method of measuring the anomalous leakage current in pass-gate MOSFET's unique to SOI devices. A high-speed measurement setup is used to provide experimental results, and to quantify the magnitude of leakage. Particularly, great care is taken to measure only the device leakage current and not the currents due to parasitic capacitances. Systematic influences of different factors such as temperature, bias, device history, and device structure on this leakage current are experimentally established,.

Transient pass-transistor leakage current in SOI MOSFET's

In this paper we experimentally demonstrate that the switching speed of digital circuits built from Non-Fully Depleted (NFD) SOI MOSFETs show a time dependence. Using a very high-bandwidth setup and pulses as short as 1 nsec, the magnitude and range of this memory effect are determined. It is demonstrated that the propagation delay variations have switching-history, V/sub dd/, and L/sub eff/ dependence. The cause of this behavior is traced to the SOI MOSFET's floating body and the dynamic variations of its stored charge and potential.

History dependence of non-fully depleted (NFD) digital SOI circuits

For pt.III see ibid., vol.SC14, no.2, p.255 (1979). An approach is described for determining the hot-electron-limited voltages for silicon MOSFETs of small dimensions. The approach was followed in determining the room-temperature and the 77K hot-electron-limited voltages for a device designed to have a minimum channel length of 1 /spl mu/m. The substrate hot-electron limits were determined empirically from measurements of the emission probabilities as a function of voltage using devices of reentrant geometry. The channel hot-electron limits were determined empirically from measurements of the injection current as a function of voltage and from long-term stress experiments.

R.H. Dennard

Papers

CMOS with active well bias for low-power and RF/analog applications

A self-aligned 1-µm-channel CMOS technology with retrograde n-well and thin epitaxy

Transient pass-transistor leakage current in SOI MOSFET's

History dependence of non-fully depleted (NFD) digital SOI circuits

1 /spl mu/m MOSFET VLSI technology. IV. Hot-electron design constraints

R.H. Dennard

Papers

CMOS with active well bias for low-power and RF/analog applications

A self-aligned 1-&#181;m-channel CMOS technology with retrograde n-well and thin epitaxy

Transient pass-transistor leakage current in SOI MOSFET's

History dependence of non-fully depleted (NFD) digital SOI circuits

1 /spl mu/m MOSFET VLSI technology. IV. Hot-electron design constraints

A self-aligned 1-µm-channel CMOS technology with retrograde n-well and thin epitaxy