Showing papers by "Robert A. Reed published in 2005"

The contribution of nuclear reactions to heavy ion single event upset cross-section measurements in a high-density SEU hardened SRAM

Abstract: Heavy ion irradiation was simulated using a Geant4 based Monte-Carlo transport code. Electronic and nuclear physics were used to generate statistical profiles of charge deposition in the sensitive volume of an SEU hardened SRAM. Simulation results show that materials external to the sensitive volume can affect the experimentally measured cross-section curve.

Autonomous bit error rate testing at multi-gbit/s rates implemented in a 5AM SiGe circuit for radiation effects self test (CREST)

Abstract: SEE testing at multi-Gbit/s data rates has traditionally involved elaborate high speed test equipment setups for at-speed testing. We demonstrate a generally applicable self test circuit approach implemented in IBM's 5AM SiGe process, and describe its ability to capture complex error signatures during circuit operation at data rates exceeding 5 Gbit/s. Comparisons of data acquired with FPGA control of the CREST ASIC versus conventional bit error rate test equipment validate the approach. In addition, we describe SEE characteristics of the IBM 5AM process implemented in five variations of the D flip-flop based serial register. Heavy ion SEE data acquired at angles follow the traditional RPP-based analysis approach in one case, but deviate by orders on magnitude in others, even though all circuits are implemented in the same 5AM SiGe HBT process.

Role of heavy-ion nuclear reactions in determining on-orbit single event error rates

Abstract: Simulations show that neglecting ion-ion interaction processes (both particles having Z>1) results in an underestimation of the total on-orbit single event upset error rate by more than two orders of magnitude for certain technologies. The inclusion of ion-ion nuclear reactions leads to dramatically different SEU error rates for CMOS devices containing high Z materials compared with direct ionization by the primary ion alone. Device geometry and material composition have a dramatic effect on charge deposition in small sensitive volumes for the spectrum of ion energies found in space, compared with the limited range of energies typical of ground tests.

The effect of metallization Layers on single event susceptibility

Abstract: We investigate the effects of metallization layers on the radiation hardness of an epitaxial CMOS memory technology using Monte Carlo simulations. A geometrically and compositionally realistic three-layer metallization scheme is employed in detailed radiation transport simulations that include contributions from discrete /spl delta/-rays and nuclear reactions. The presence of high-Z plugs used to connect different metallization layers can have a significant effect on the single-event sensitivity depending on the location of the high-Z material relative to the sensitive region of the underlying device.

Hot pixel annealing behavior in CCDs irradiated at -84/spl deg/C

Abstract: A Hubble space telescope wide field camera 3 e2v CCD was irradiated while operating at -84/spl deg/C and the dark current studied as a function of temperature while the charge coupled device was warmed to a sequence of temperatures up to a maximum of +30/spl deg/C. The device was then cooled back down to -84/spl deg/ and remeasured. Hot pixel populations were tracked during the warm up and cool down. Hot pixel annealing began below -40/spl deg/C and the anneal process was largely completed by the time the detector reached +20/spl deg/C. There was no apparent sharp annealing temperature. Although a large fraction of the hot pixels fell below the threshold to be counted as a hot pixel, they nevertheless sustained a higher leakage rate than the remaining population. The mechanism for hot pixel annealing is not presently understood. Room temperature irradiations do not adequately characterize the hot pixel distributions for cooled applications.

Simulation of a new back junction approach for reducing charge collection in 200 GHz SiGe HBTs

Abstract: We present a new back junction approach for reducing SEU-induced charge collection in SiGe HBTS, and demonstrate its effectiveness in a state-of-the-art 200 GHz SiGe HBT using full 3-D device simulation. An additional n/sup +/ layer is used below the p-type isolation layer to form a back junction. The back junction limits potential funneling to within the p-type layer, which effectively limits the total amount of drift charge collection that is now shared by the collector-to-substrate junction and the back junction. The back junction also cuts off the diffusion charge coming from the substrate, further limiting charge collection by the HBT collector. A thinner p-type "substrate" layer and a better contact to the added n/sup +/ layer are shown to help reduce charge collection by the HBT collector, the sensitive node.

Transient radiation effects in ultra-low noise HgCdTe IR detector arrays for space-based astronomy

Abstract: We present measurements of proton-induced single event transients in ultra-low noise HgCdTe IR detector arrays being developed for space-based astronomy and compare to modeling results.

Simulating Nuclear Events in a TCAD Model of a High-Density SEU Hardened SRAM Technology

Abstract: The interaction between a heavy ion and the overlayer materials in an integrated circuit may result in a nuclear reaction. This reaction leads to a charge generation profile that is substantially altered from the profile generated during a direct ionization event. In this work, nuclear reactions are integrated into the modeling of the SEU response of an SRAM cell using GEANT4-based simulations. The simulated transient response is compared to the response obtained using a typical heavy ion model that includes only direct ionization

Recent radiation issues in silicon-on-insulator devices

Abstract: Scaling to lower voltages, thinner layers, new materials, and multi-gate structures has implications for radiation effects in microelectronics, including SOI-based devices. Shorter channel lengths increase the parasitic bipolar gain and thinner BOX layers exacerbate capacitive coupling from charge deposited in the substrate. Thinner silicon layers may reduce charge collection, but place the BOX layer in closer proximity to the device channel, increasing the relevance of the total-ionizing-dose radiation response of the BOX layer and associated interfaces. Technology roadmaps include SiGe HBTs and non-planar multi-gate CMOS structures on SOI. This paper discusses recent radiation issues in SOI devices, and implications of new device structures and materials, and smaller dimensions, for radiation effects in future SOI devices.