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Design Of Analog Cmos Integrated Circuits

Thank you very much for downloading design of analog cmos integrated circuits. Maybe you have knowledge that, people have look hundreds times for their favorite novels like this design of analog cmos integrated circuits, but end up in malicious downloads. Rather than reading a good book with a cup of coffee in the afternoon, instead they cope with some malicious virus inside their laptop. design of analog cmos integrated circuits is available in our book collection an online access to it is set as public so you can download it instantly. Our digital library saves in multiple countries, allowing you to get the most less latency time to download any of our books like this one. Merely said, the design of analog cmos integrated circuits is universally compatible with any devices to read.

We present the first all-digital PLL and polar transmitter for mobile phones. They are part of a single-chip GSM/EDGE transceiver SoC fabricated in a 90 nm digital CMOS process. The circuits are architectured from the ground up to be compatible with digital deep-submicron CMOS processes and be readily integrateable with a digital baseband and application processor. To achieve this, we exploit the new paradigm of a deep-submicron CMOS process environment by leveraging on the fast switching times of MOS transistors, the fine lithography and the precise device matching, while avoiding problems related to the limited voltage headroom. The transmitter architecture is fully digital and utilizes the wideband direct frequency modulation capability of the all-digital PLL. The amplitude modulation is realized digitally by regulating the number of active NMOS transistor switches in accordance with the instantaneous amplitude. The conventional RF frequency synthesizer architecture, based on a voltage-controlled oscillator and phase/frequency detector and charge-pump combination, has been replaced with a digitally controlled oscillator and a time-to-digital converter. The transmitter performs GMSK modulation with less than 0.5/spl deg/ rms phase error, -165 dBc/Hz phase noise at 20 MHz offset, and 10 /spl mu/s settling time. The 8-PSK EDGE spectral mask is met with 1.2% EVM. The transmitter occupies 1.5 mm/sup 2/ and consumes 42 mA at 1.2 V supply while producing 6 dBm RF output power.

/pdf/all-digital-pll-and-transmitter-for-mobile-phones-2mf5fxyzjo.pdf

All-digital PLL and transmitter for mobile phones

We present a single-chip fully compliant Bluetooth radio fabricated in a digital 130-nm CMOS process. The transceiver is architectured from the ground up to be compatible with digital deep-submicron CMOS processes and be readily integrated with a digital baseband and application processor. The conventional RF frequency synthesizer architecture, based on the voltage-controlled oscillator and the phase/frequency detector and charge-pump combination, has been replaced with a digitally controlled oscillator and a time-to-digital converter, respectively. The transmitter architecture takes advantage of the wideband frequency modulation capability of the all-digital phase-locked loop with built-in automatic compensation to ensure modulation accuracy. The receiver employs a discrete-time architecture in which the RF signal is directly sampled and processed using analog and digital signal processing techniques. The complete chip also integrates power management functions and a digital baseband processor. Application of the presented ideas has resulted in significant area and power savings while producing structures that are amenable to migration to more advanced deep-submicron processes, as they become available. The entire IC occupies 10 mm/sup 2/ and consumes 28 mA during transmit and 41 mA during receive at 1.5-V supply.

https://users.ece.utexas.edu/~adnan/comm-08/bluetooth-jssc-04.pdf

All-digital TX frequency synthesizer and discrete-time receiver for Bluetooth radio in 130-nm CMOS

This paper presents the design of a coarse-fine time-to-digital converter (TDC) that amplifies a time residue to improve time resolution, similar to a coarse-fine analog-to-digital converter (ADC). A new digital circuit has been developed to amplify the time residue with a higher gain (>16) and larger range (>80 ps) than existing solutions do. However, adapting the conventional coarse-fine architecture from ADCs is not an appropriate solution for TDCs: input time cannot be stored, and the gain of a time amplifier (TA) cannot be controlled precisely. This paper proposes a new coarse-fine TDC architecture by using an array of time amplifiers and two identical fine TDCs that compensate for the variation of the TA gain during the conversion process. The measured DNL and INL are plusmn0.8 LSB and plusmn3 LSB, respectively, with a value of 1.25 ps per 1 LSB, while the standard deviation of output code for constant inputs remains below 1 LSB across the TDC range. Although the nonlinearity is larger than 1 LSB, using an INL lookup table or better matched delays in the coarse TDC delay chain will improve the linearity further.

A 9 b, 1.25 ps Resolution Coarse–Fine Time-to-Digital Converter in 90 nm CMOS that Amplifies a Time Residue

Precise modeling and understanding of all nonlinear characteristics in radio-frequency (RF) CMOS circuits is a pre-requisite to the successful integration of modern CMOS radios. This paper summarizes a harmonic characterization techniques used to estimate the mismatches in the minimal size inversion-type CMOS tuning varactors of a digitally controlled RF oscillator (DCO). The DCO is the centerpiece of the first ever all-digital phase locked loop (ADPLL) fabricated in 90 nm digital CMOS that meets the challenging GSM performance specifications. Full-scale VHDL simulations as well as lab measurements confirm that the tracking bank varactors have a better than 5% mismatch, thus contributing to the excellent modulation performance of the RF chip

Harmonic characterization of mismatches in deep sub-micron varactors for a digitally controlled RF oscillator

The present invention provides a method and an apparatus of calibrating mismatches of a time-to-digital converter (TDC). The method includes: capturing phase error samples; calculating difference between the phase error samples and an expected value of the phase error samples; and adjusting correction gain of the TDC based on the calculating step. Another method of calibrating mismatches of a TDC includes: capturing TDC output code samples; storing a plurality of accumulation values corresponding to different TDC values respectively, wherein each accumulation value records a number of times a TDC value is carried by the TDC output code samples; calculating a desired value based on the accumulation values; calculating difference between the accumulation values and the desired value; and adjusting correction gain of the TDC based on the calculating step. The present invention also provides the apparatus of calibrating the mismatches of the TDC. The present invention can save chip area and power consumption.

Method and apparatus of calibrating mismatch of TDC

An RF receiver front-end for a GSM/GPRS radio system-on-chip in a 90nm digital CMOS technology is presented. The circuit consisting of low noise amplifier, transconductance amplifier, switching mixer and local oscillator, offers 32.5dB dynamic range of gain control that is digitally configurable. Even under the digital spurious noise, the noise figure in the 40dB maximum gain is 1.8dB and +50dBm IIP2 in 34dB gain. The variation of the input matching versus multiple gains is less than 1dB. The local oscillator to drive the mixer fulfills the stringent phase noise requirement of -153.5 dBc/Hz at 3-MHz. The circuit occupies 1.62mm. The LNA, TA and mixer consume less than 15.3mA at a supply voltage of 1.4V.

/pdf/a-1-8db-nf-receiver-front-end-for-gsm-gprs-in-a-90nm-digital-58x50otp0p.pdf

A 1.8dB NF Receiver front-end for GSM/GPRS in a 90nm Digital CMOS

A multi-stage digitally-controlled power amplifier (DPA) includes a radio-frequency (RF) clock input, an amplitude control word (ACW) input, a plurality of drivers, and an output stage. The RF clock input is arranged for receiving an RF clock. The ACW input is arranged for receiving a digital ACW signal. The drivers are coupled to the RF clock, and arranged for producing a plurality of intermediate signals, wherein at least one driver of the drivers is responsive to at least one bit of the digital ACW signal. The output stage is coupled to the intermediate signals, and arranged for producing an output signal.

Multi-stage digitally-controlled power amplifier

A method and system for performing a timing recovery acquisition of a sinusoidal preamble with reduced loop latency by effectively bypassing the FIR filter out of the timing loop. The method is implemented by estimating the FIR filter's ( 201 ) phase shift through knowing its coefficients a priori while also determining the phase error at the FIR filter's input. Because of the non-symmetric settings of the coefficients the phase shift through the FIR may not be zero. It reduces the latency of a non-data tracking timing loop by eliminating latency due to the FIR filter ( 201 ) itself. The coefficients can be either programmed in memory ( 205 ) or adapted as part of an LMS application. The estimate avoids the use of multiply operations, using add operations and a single divider. The estimated partial phase errors are then summed in a “FIR bypass-mode” phase detector ( 204 ) yielding total phase shift.

Robert Bogdan Staszewski

Papers

Harmonic characterization of mismatches in deep sub-micron varactors for a digitally controlled RF oscillator

Method and apparatus of calibrating mismatch of TDC

A 1.8dB NF Receiver front-end for GSM/GPRS in a 90nm Digital CMOS

Multi-stage digitally-controlled power amplifier

Phase-shift calculation method, and system implementing it, for a finite-impulse-response (FIR) filter