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Design Of Analog Cmos Integrated Circuits

Thank you very much for downloading design of analog cmos integrated circuits. Maybe you have knowledge that, people have look hundreds times for their favorite novels like this design of analog cmos integrated circuits, but end up in malicious downloads. Rather than reading a good book with a cup of coffee in the afternoon, instead they cope with some malicious virus inside their laptop. design of analog cmos integrated circuits is available in our book collection an online access to it is set as public so you can download it instantly. Our digital library saves in multiple countries, allowing you to get the most less latency time to download any of our books like this one. Merely said, the design of analog cmos integrated circuits is universally compatible with any devices to read.

We present the first all-digital PLL and polar transmitter for mobile phones. They are part of a single-chip GSM/EDGE transceiver SoC fabricated in a 90 nm digital CMOS process. The circuits are architectured from the ground up to be compatible with digital deep-submicron CMOS processes and be readily integrateable with a digital baseband and application processor. To achieve this, we exploit the new paradigm of a deep-submicron CMOS process environment by leveraging on the fast switching times of MOS transistors, the fine lithography and the precise device matching, while avoiding problems related to the limited voltage headroom. The transmitter architecture is fully digital and utilizes the wideband direct frequency modulation capability of the all-digital PLL. The amplitude modulation is realized digitally by regulating the number of active NMOS transistor switches in accordance with the instantaneous amplitude. The conventional RF frequency synthesizer architecture, based on a voltage-controlled oscillator and phase/frequency detector and charge-pump combination, has been replaced with a digitally controlled oscillator and a time-to-digital converter. The transmitter performs GMSK modulation with less than 0.5/spl deg/ rms phase error, -165 dBc/Hz phase noise at 20 MHz offset, and 10 /spl mu/s settling time. The 8-PSK EDGE spectral mask is met with 1.2% EVM. The transmitter occupies 1.5 mm/sup 2/ and consumes 42 mA at 1.2 V supply while producing 6 dBm RF output power.

/pdf/all-digital-pll-and-transmitter-for-mobile-phones-2mf5fxyzjo.pdf

All-digital PLL and transmitter for mobile phones

We present a single-chip fully compliant Bluetooth radio fabricated in a digital 130-nm CMOS process. The transceiver is architectured from the ground up to be compatible with digital deep-submicron CMOS processes and be readily integrated with a digital baseband and application processor. The conventional RF frequency synthesizer architecture, based on the voltage-controlled oscillator and the phase/frequency detector and charge-pump combination, has been replaced with a digitally controlled oscillator and a time-to-digital converter, respectively. The transmitter architecture takes advantage of the wideband frequency modulation capability of the all-digital phase-locked loop with built-in automatic compensation to ensure modulation accuracy. The receiver employs a discrete-time architecture in which the RF signal is directly sampled and processed using analog and digital signal processing techniques. The complete chip also integrates power management functions and a digital baseband processor. Application of the presented ideas has resulted in significant area and power savings while producing structures that are amenable to migration to more advanced deep-submicron processes, as they become available. The entire IC occupies 10 mm/sup 2/ and consumes 28 mA during transmit and 41 mA during receive at 1.5-V supply.

https://users.ece.utexas.edu/~adnan/comm-08/bluetooth-jssc-04.pdf

All-digital TX frequency synthesizer and discrete-time receiver for Bluetooth radio in 130-nm CMOS

This paper presents the design of a coarse-fine time-to-digital converter (TDC) that amplifies a time residue to improve time resolution, similar to a coarse-fine analog-to-digital converter (ADC). A new digital circuit has been developed to amplify the time residue with a higher gain (>16) and larger range (>80 ps) than existing solutions do. However, adapting the conventional coarse-fine architecture from ADCs is not an appropriate solution for TDCs: input time cannot be stored, and the gain of a time amplifier (TA) cannot be controlled precisely. This paper proposes a new coarse-fine TDC architecture by using an array of time amplifiers and two identical fine TDCs that compensate for the variation of the TA gain during the conversion process. The measured DNL and INL are plusmn0.8 LSB and plusmn3 LSB, respectively, with a value of 1.25 ps per 1 LSB, while the standard deviation of output code for constant inputs remains below 1 LSB across the TDC range. Although the nonlinearity is larger than 1 LSB, using an INL lookup table or better matched delays in the coarse TDC delay chain will improve the linearity further.

A 9 b, 1.25 ps Resolution Coarse–Fine Time-to-Digital Converter in 90 nm CMOS that Amplifies a Time Residue

/pdf/digital-deep-submicron-cmos-frequency-synthesis-for-rf-1t4jxlp23z.pdf

Digital Deep-Submicron CMOS Frequency Synthesis for RF Wireless Appllications

We present a new all-digital RF in-phase/quadrature (I/Q) modulator, in which the orthogonal summing of the I and Q phase data signals is performed in separated interleaved time slots. By employing a 25% duty cycle for the I and Q signals, the modulator can directly reconstruct the continuous-time RF output signal using four digital switch arrays with a power combiner. To verify the proposed concept and its related design procedure, a 65-nm CMOS prototype is implemented. This prototype achieves 12.6-dBm peak output power with 20% peak drain efficiency at 2 GHz. The corresponding error vector magnitude (EVM) for a quadrature phase-shift keying constellation is 3.95% without any predistortion, while providing 6-dBm output power in a 64 quadrature amplitude modulation constellation with a related EVM and drain efficiency of 2.36% and 10%, respectively. The proposed circuit can be used as a pre-driver or a final transmit stage. The first-ever truly all-digital I/Q RF digital-to-analog converter prototype is thus experimentally demonstrated.

All-Digital RF $I/Q$ Modulator

This paper investigates design considerations and challenges of integrating on-chip antennas in nanoscale CMOS technology at millimeter-wave (mm-wave) to achieve a compact front-end receiver for 5G communication systems. Solutions to overcome these challenges are offered and realized in digital 28-nm CMOS. A monolithic on-chip antenna is designed and optimized in the presence of rigorous metal density rules and other back-end-of-the-line (BEoL) challenges of the nanoscale technology. The proposed antenna structure further exploits ground metallization on a PCB board acting as a reflector to increase its radiation efficiency and power gain by 37.3% and 9.8 dB, respectively, while decreasing the silicon area up to 30% compared to the previous works. The antenna is directly matched to a two-stage low noise amplifier (LNA) in a synergetic way as to give rise to an active integrated antenna (AIA) in order to avoid additional matching or interconnect losses. The LNA is followed by a double-balanced folded Gilbert cell mixer, which produces a lower intermediate frequency (IF) such that no probing is required for measurements. The measured total gain of the AIA is 14 dBi. Its total core area is 0.83 mm
 2
 while the total chip area, including the pad frame, is 1.55 × 0.85 mm
 2
.

/pdf/challenges-in-on-chip-antenna-design-and-integration-with-rf-872an50q2l.pdf

Challenges in On-Chip Antenna Design and Integration with RF Receiver Front-End Circuitry in Nanoscale CMOS for 5G Communication Systems

RF circuits for multi-GHz frequencies have recently migrated to low-cost digital deep-submicron CMOS processes Unfortunately, this process environment, which is optimized only for digital logic and SRAM memory, is extremely unfriendly for conventional analog and RF designs We present fundamental techniques recently developed that transform the RF and analog circuit design complexity to digitally intensive domain for a wireless RF transceiver, so that it enjoys benefits of digital and switched-capacitor approaches Direct RF sampling techniques allow great flexibility in reconfigurable radio design Digital signal processing concepts are used to help relieve analog design complexity, allowing one to reduce cost and power consumption in a reconfigurable design environment The ideas presented have been used in Texas Instruments to develop two generations of commercial digital RF processors: a single-chip Bluetooth radio and a single-chip GSM radio We further present details of the RF receiver front end for a GSM radio realized in a 90-nm digital CMOS technology The circuit consisting of low-noise amplifier, transconductance amplifier, and switching mixer offers 325 dB dynamic range with digitally configurable voltage gain of 40 dB down to 75dB A series of decimation and discrete-time filtering follows the mixer and performs a highly linear second-order lowpass filtering to reject close-in interferers The front-end gains can be configured with an automatic gain control to select an optimal setting to form a trade-off between noise figure and linearity and to compensate the process and temperature variations Even under the digital switching activity, noise figure at the 40 dB maximum gain is 18 dB and +50 dBm IIP2 at the 34 dB gain The variation of the input matching versus multiple gains is less than 1 dB The circuit in total occupies 31 mm2  The LNA, TA, and mixer consume less than 153 mA at a supply voltage of 14 V

/pdf/charge-domain-signal-processing-of-direct-rf-sampling-mixer-4d98jbz1yj.pdf

Charge-domain signal processing of direct RF sampling mixer with discrete-time filters in Bluetooth and GSM receivers

A transmitter employing a sigma delta modulator having a noise transfer function adapted to shift quantization noise outside at least one frequency band of interest. A technique is presented to synthesize the controllers within a single-loop sigma delta modulator such that the noise transfer function can be chosen arbitrarily from a family of functions satisfying certain conditions. Using the novel modulator design technique, polar and Cartesian (i.e. quadrature) transmitter structures are supported. A transmitter employing polar transmit modulation is presented that shapes the spectral emissions of the digitally-controlled power amplifier such that they are significantly and sufficiently attenuated in one or more desired frequency bands. Similarly, a transmitter employing Cartesian transmit modulation is presented that shapes the spectral emissions of a hybrid power amplifier such that they are significantly and sufficiently attenuated in one or more desired frequency bands.

Robert Bogdan Staszewski

Papers

Digital Deep-Submicron CMOS Frequency Synthesis for RF Wireless Appllications

All-Digital RF $I/Q$ Modulator

Challenges in On-Chip Antenna Design and Integration with RF Receiver Front-End Circuitry in Nanoscale CMOS for 5G Communication Systems

Charge-domain signal processing of direct RF sampling mixer with discrete-time filters in Bluetooth and GSM receivers

Transmitter for wireless applications incorporation spectral emission shaping sigma delta modulator