Robert Bogdan Staszewski

TL;DR: In this paper, a phase locked loop circuit (30, 100, 110 ) was proposed for generating an output signal of desired frequency responsive to a control signal, which is driven by the outputs of the first and second phase detections circuits.

TL;DR: The receiver in the first single-chip GSM transceiver that incorporates full integration of quad-band receiver, transmitter, memory, power management, dedicated ARM processor and RF built-in self test in a 90 nm digital CMOS process is presented.

TL;DR: In this paper, the authors proposed a method of spur reduction using computation spreading with dithering in a digital phase-locked loop (DPLL) architecture, where a software-based PLL incorporates a reconfigurable calculation unit (RCU) that is optimized and programmed to sequentially perform all the atomic operations of a PLL or any other desired task in a time sharing manner.

TL;DR: This paper proposes a digital-to-time converter (DTC)-assisted fractional-N wide-bandwidth all-digital phase-locked loop (ADPLL) with a fine-resolution time- to-digital converter (TDC), which employs a two-channel time-interleaved time-domain register with an implicit adder/subtractor realizing an error-feedback topology.

TL;DR: In this article, a bank of more significant binary-weighted and/or less significant equally weighted capacitors that are switched between only two voltage potentials is determined by dithering between the two states to achieve a further refinement in the resolution of the resonating frequency.