Since Moore’s law driven scaling of planar MOSFETs
faces formidable challenges in the nanometer regime, FinFETs and Trigate FETs have emerged as their successors. Owing
to the presence of multiple (two/three) gates, FinFETs/Trigate
FETs are able to tackle short-channel effects (SCEs) better than
conventional planar MOSFETs at deeply scaled technology nodes
and thus enable continued transistor scaling. In this paper, we
review research on FinFETs from the bottommost device level
to the topmost architecture level. We survey different types of
FinFETs, various possible FinFET asymmetries and their impact,
and novel logic-level and architecture-level tradeoffs offered by
FinFETs. We also review analysis and optimization tools that
are available for characterizing FinFET devices, circuits, and
architectures.

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FinFETs: From Devices to Architectures

The explosive growth of smart mobile wireless devices in recent years has fundamentally transformed the semiconductor industry. Mobile system-on-chips (SoCs) has become the leading product driver for technology definition and manufacturing for the semiconductor industry. This trend was first observed in 28 nm and will continue for 20 nm, 16/14 nm, and 10 nm adoption and production ramp. Recent mobile SoC performance increase was achieved mainly through silicon technology scaling, and from single to dual- and quad-core. For mobile SoCs to continue offering new and exciting user-experiences, and longer battery life, a holistic approach in orthogonal system scaling to break out of the box of (speed*density/power/cost) constrains is mandated. Examples in the new paradigm of mobile heterogeneous computing are: energy-efficient transistors/memories/interconnects in expanding and boosting existing SoC functionalities (e.g., SiGe/III-V FinFET, GAA-FET, TFET, and RRAM/MRAM etc.), all-inclusive technology/design co-optimization to extract more values from silicon tech, RFFE system integration, and the multi-die integration by system partitioning that allows each component to be optimized and integrated closely together for lower cost and power, higher performance, and reduced form factor. Numerous challenges are ahead yet tremendous opportunities exist for collaborative and multiplicative innovations in the industry to enable the continued growth of mobile SoCs.

Smart mobile SoCs driving the semiconductor industry: Technology trend, challenges and opportunities

Influence of fin width downscaling on hole and electron mobility behavior in FinFETs with (1 0 0), (1 1 0) and (1 1 1) oriented sidewalls is examined. Our effective-mass model reproduces experimental results of UTB SOI pMOSFETs fabricated on (1 0 0) and (1 1 0) surfaces, including the effect of mobility enhancement for certain body thicknesses in (1 1 0) oriented devices. The suitability of well-calibrated EMA for the simulation of hole mobility is confirmed by our results, which opens a possibility of using hole EMA in advanced Monte Carlo simulators. Simulations show that with the downscaling of fin width nFinFETs with (1 0 0) sidewalls and pFinFETs with (1 1 0) and (1 1 1) sidewalls exhibit mobility enhancement in certain fin-width ranges. In contrast, other FinFET configurations experience monotonic mobility degradation with the decreasing fin width. Regarding experimental (1 1 1) FinFETs from our previous work, modeling results suggest that the fin width is highly uniform along the channel, both in nFinFETs and pFinFETs. The impact of electron and hole mobility behavior in UTB FinFETs on SRAM design is also studied. We have found that FinFETs with (1 1 1) active surface enable the most efficient use of the layout area, demanding only four fins for an SRAM cell with matched inverters and high immunity to noise.

Modeling study on carrier mobility in ultra-thin body FinFETs with circuit-level implications

When CMOS technologies enter nanometer scale, FinFET has become one of the most promising devices because of the superior electrical characteristics. Nonetheless, due to the scaling of dielectric thickness and the occurring of line-edge roughness, FinFETs may suffer the gate oxide short. Gate oxide short is a defect that has been widely discussed in planar bulk MOSFETs. But for FinFETs, the defect characteristics have not been studied yet. In this paper, we investigate the fault behaviors of the gate oxide short in FinFETs. The investigation includes both tied-gate and independent-gate FinFETs. Based on the TCAD mixed-mode simulations, we discover that the gate oxide short in the two types of FinFETs causes different fault behaviors from each other. Compared to planar bulk MOSFETs, the fault behaviors are even more complex. In addition to the discussion at device level, we also discuss the corresponding SRAM testing. For detecting gate oxide short in FinFET SRAMs, we propose two new test methods. By using TCAD transient simulations, we prove the two methods' test efficacy of detecting the gate oxide shorts uncovered by traditional test methods.

Investigation of gate oxide short in FinFETs and the test methods for FinFET SRAMs

Negative bias temperature instability (NBTI) reliability in p-FinFET devices is studied with respect to the silicon substrate orientation. Interface trap density Nit is lower in the 45° rotated devices compared with the 0° rotated devices because of lower density of Si dangling bond at the (100) side walls than the (110) side walls. This improves NBTI reliability in the 45° rotated FinFET devices. Furthermore, we demonstrate that the lower inversion charge density Ninv-exhibited when transitioning from planar to FinFET architecture at 45° rotation-plays an important role in the whole NBTI degradation. NBTI clearly improves in the 45° rotated FinFET devices compared with the planarlike device because of the lower Ninv. Leakage current density analysis is shown as an experimental proof, in addition to simulation results of Cho et al.

Negative Bias Temperature Instability in p-FinFETs With 45 $^{\circ}$ Substrate Rotation

In this paper, the design space, including fin thickness (Tfin), fin height (Hfin), fin ratio of bit-cell transistors, and surface orientation, is researched to optimize the stability, leakage current, array dynamic energy, and read/write delay of the FinFET SRAM under layout area constraints. The simulation results, which consider the variations of both Tfin and threshold voltage (Vth), show that most FinFET SRAM configurations achieve a superior read/write noise margin when compared with planar SRAMs. However, when two fins are used as pass gate transistors (PG) in FinFET SRAMs, enormous array dynamic energy is required due to the increased effective gate and drain capacitance. On the other hand, a FinFET SRAM with a one-fin PG in the (110) plane shows a smaller write noise margin than the planar SRAM. Thus, the one-fin PG in the (100) plane is suitable for FinFET SRAM design. The one-fin PG FinFET SRAM with Tfin = 10 nm and Hfin = 40 nm in the (100) plane achieves a three times larger noise margin when compared with the planar SRAM and consumes a 17% smaller bit-line toggling array energy at a cost of a 22% larger word-line toggling energy. It also achieves a 2.3 times smaller read delay and a 30% smaller write delay when compared with the planar SRAM.

FinFET SRAM Optimization With Fin Thickness and Surface Orientation

Supply voltage (Vcc) scaling is mostly used method to achieve low power consumption. However, a high Vccmin is required to meet the high target yield because the SRAM yield according to Vcc scaling shows “dual slope”. In this paper, the root causes of “dual slope” are analyzed. Both side effect of SRAM bitcell on the yield is also considered to accurately project Vccmin, which results in 40mV increase of Vccmin to meet 99% target yield for 32nm HK/MG planar 1M SRAM. The “dual slope” effect on the yield is compared for 32nm HK/MG planar and FinFET 32M SRAMs with high (HD) and low doping (LD). Under the “dual slope” effect, the channel length adjustment method for pass gate transistor is proposed to reduce Vccmin of FinFET SRAM. When the number of finis is 1∶2∶2(=PU∶PG∶PD), HD and LD 32M FinFET SRAMs improve Vccmin by 370mV and 500mV, respectively, compared to 32M planar counterparts using the proposed the channel length adjustment method. Effect of NBTI and PBTI on Vccmin is also investigated. BTI degradation is greatly dependent on HK thickness and surface plane orientation of FinFET. End of Life (EOL) Vccmin optimization therefore requires careful selection of HK thickness and surface orientation.

S. H. Woo

Papers

FinFET SRAM Optimization With Fin Thickness and Surface Orientation

Accurate projection of V ccmin by modeling “dual slope” in FinFET based SRAM, and impact of long term reliability on end of life V ccmin