Ultrathin ZrO2 gate dielectrics have been deposited on strain-compensated Si0.69Ge0.3C0.01 layers by rf magnetron sputtering. High-resolution transmission electron microscopy along with energy-dispersive x-ray spectroscopy and x-ray photoelectron spectroscopy show the formation of a polycrystalline ZrO2 and an amorphous Zr–germano–silicate interfacial layer between the deposited oxide and SiGeC films. A dielectric constant of 17.5 for ZrO2 and 7.0 for an interfacial-silicate layer have been calculated from the high-frequency capacitance–voltage measurements. These dielectrics show an equivalent oxide thickness as low as 1.9 nm for ZrO2 and 2.0 nm for the interfacial silicate layer. An extremely low leakage current density of ∼9×10−8 A/cm2 at a gate voltage of −1.0 V, breakdown field of 7 MV/cm and moderate interface state density of 6×1011 cm−2 eV−1 have been obtained for the fabricated capacitors.

Electrical and interfacial characteristics of ultrathin ZrO2 gate dielectrics on strain compensated SiGeC/Si heterostructure

Capacitance–voltage (C–V) characteristics are used to investigate double heterojunction strained Si/SiGe MOS capacitors. Structures of this type potentially form the channels of CMOS devices based on the strained Si/SiGe material system. The technique represents a fast and non-destructive method to determine important characteristics such as layer thicknesses, threshold voltages and band offsets. Moreover, it contributes to the design of optimum heterostructures for CMOS. Experimental C–V data are compared with simulation and complementary results including SIMS and TEM to confirm the accuracy of the technique.

C–V characterization of strained Si/SiGe multiple heterojunction capacitors as a tool for heterojunction MOSFET channel design

Very exciting and promising results from recent developments in group-IV alloy heterostructures (viz., SiGe, SiGeC, SiC, GeC and strained-Si) have led to the belief that SiGe-based devices will open up an entirely new dimension to the future of VLSI/ULSI technology. The growth of ultrathin dielectric films on a strained group-IV alloy layer is a challenging task. As metal-oxide-semiconductor devices are being aggressively scaled down, high permittivity dielectrics are being widely investigated as alternative gate insulating layers in advanced MOS devices. The present paper reviews the recent results of different gate and high-k dielectrics on group-IV alloy layers for scaled CMOS devices, high-mobility pure-Ge channel devices and nanocrystal floating gate memories.

High-k gate oxide for silicon heterostructure MOSFET devices

We have fabricated strained SiGe vertical P-channel and N-channel metal-oxide-semiconductor field-effect transistors (MOSFETs) by Ge ion implantation and solid phase epitaxy. No Si cap is needed in this process because Ge is implanted after gate oxide growth. The vertical MOSFETs are fabricated with a channel length below 0.2 /spl mu/m without sophisticated lithography and the whole process is compatible with a regular CMOS process. The enhancement for the hole and electron mobilities in the direction normal to the growth plane of strained SiGe over that of bulk Si has been demonstrated in this vertical MOSFET device structure for the first time. The drain current for the vertical SiGe MOSFETs has been found to be enhanced by as much as 100% over the Si control devices and the drain current for the vertical SiGe NMOSFETs has been enhanced by 50% compared with the Si control de, ices on the same wafer. The electron mobility enhancement in the normal direction is not as significant as that for holes, which is in agreement with theoretical predictions.

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Hole and electron mobility enhancement in strained SiGe vertical MOSFETs

We investigate the effects of silicon cap layer thinning on channel carrier confinement in silicon/strained silicon-germanium (Si/SiGe) metal–oxide–semiconductor (MOS) structures. The silicon cap thickness is shown to have a critical influence on the induced parasitic channel in the silicon cap, which lowers the transconductance value of the buried SiGe channel in hole carrier channel p metal–oxide–semiconductor field-effect transistor devices. This can have serious consequences on future implementation of SiGe ultrashort channel devices where gate induced parasitic channel and short channel effects can be pronounced. An exact methodology is devised for consumption of silicon cap layer using a modified Radio Corporation of America surface standard clean self-terminating chemical oxide and rapid thermal oxide growth. This provides (i) precise control over the silicon cap and thermal oxide thickness and (ii) a limit on the amount of thermal budget induced strain relaxation in the buried SiGe layer. The threshold voltages for inversion of carriers at the SiO2/Si and the Si/SiGe interfaces are extracted as functions of Si cap thickness. A transition from dual to single channel operation in MOS devices at room temperature on thinning the silicon cap layer is observed with capacitance–voltage measurements. Cross-section transmission electron microscopy and secondary ion mass spectroscopy techniques are used to calibrate and support the developed methodology for Si cap layer etch control and the effect of Ge species at the oxide–heterostructure interface. There is a high fixed charge density, which indicates Ge pileup at the SiO2/SiGe interface. Our analysis suggests that about 1 nm of silicon cap retention is necessary to minimize the gate induced parasitic channel and to decouple the oxide interface trap influence on the channel carriers in the SiGe.

Effect of Si cap layer on parasitic channel operation in Si/SiGe metal-oxide-semiconductor structures

Pseudomorphic Si1-x
Ge
 x
 and partially strain compensated 
$${\text{Si}}_{1 - x - y} {\text{Ge}}_x {\text{C}}_y $$

 layers with different Ge and C fractions have been grown at 500 °C by ultra high vacuum chemical vapor deposition on Si (100) substrates The degree of strain compensation of the layers has been investigated by high resolution X-ray diffraction and simple application of the linear elasticity theory The surface morphology of the layers has been characterized by atomic force microscopy The dependence of Si–Si Raman mode vibrations on strain and composition of binary and ternary alloys have been explained with experimental and theoretically calculated results The Hall hole mobility is found to increase with decreasing compressive strain or effective Ge content in the layer throughout the temperature range of 120–300 K

Effect of carbon on lattice strain and hole mobility in Si1-xGex alloys

Ultra-thin oxides (<100 A) have been grown on strained Si/Si1−xGex/Si layers at a low temperature using microwave O2- and NO-plasma. Metal-oxide-semiconductor (MOS) capacitors fabricated using these oxides have been used for the determination of the hole density in the Si-cap and the Si0.8Ge0.2-channel. The valence band discontinuity (ΔEv) at the Si/Si0.8Ge0.2 heterointerface has been extracted from the carrier confinement characteristics of the quantum well. Capacitance–voltage (C–V) profiling has been used to measure the apparent doping profile and thickness of the unconsumed Si-cap layer. Fowler–Nordheim (F–N) constant current stressing shows that NO-plasma grown oxides have an improved charge trapping behavior over the O2-plasma grown oxides.

Electrical characterization of Si/Si1-xGex/Si quantum well heterostructures using a MOS capacitor

Hall mobilities in a temperature range of 80–300 K have been measured in fully strained Si1−xGex and partially strain-compensated p-type Si1−x−yGexCy alloy layers grown on Si (100) by ultrahigh vacuum chemical vapor deposition. The effect of the addition of C on strain compensation of Si1−xGex films has been studied by high-resolution x-ray diffraction analysis. The Hall hole mobility is found to increase with decreasing compensative strain or effective Ge content in the layer throughout the studied temperature range. The effect of a Si-cap layer on the hole mobility of Si1−x−yGexCy film has been investigated.

Hall mobilities in B-doped strained Si1−xGex and Si1−x−yGexCy layers grown by ultrahigh vacuum chemical vapor deposition

Ultra-thin gate oxides (<100 A) have been grown on partially strain-compensated Si/Si1-x-yGexCy/Si heterolayers (with different carbon concentrations) using microwave O2-plasma. A MOS capacitor has been used for the characterization of grown oxides. Capacitance-voltage (C-V) profiling has been used to measure the apparent doping profile and thickness of the unconsumed Si-cap layer. A significant improvement in charge trapping properties, under Fowler-Nordheim (F-N) constant current stressing, has been observed for low carbon containing films. The valence band offsets (ΔEv) of Si/Si0.69Ge0.3C0.01 and Si/Si0.685Ge0.3C0.015 heterostructures have been extracted using the hole confinement characteristics. Incorporation of C lowers the valence band offset of the ternary alloy compared to those in Si1-xGex with the same Ge mole fraction.

S. John

Papers

Effect of carbon on lattice strain and hole mobility in Si1-xGex alloys

Electrical characterization of Si/Si1-xGex/Si quantum well heterostructures using a MOS capacitor

Hall mobilities in B-doped strained Si1−xGex and Si1−x−yGexCy layers grown by ultrahigh vacuum chemical vapor deposition

Electrical characterization of ultra-thin gate oxides on Si/Si1-x-yGexCy/Si quantum well heterostructures