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Anindya Sundar Dhar

Researcher at Indian Institute of Technology Kharagpur

Publications -  154
Citations -  1362

Anindya Sundar Dhar is an academic researcher from Indian Institute of Technology Kharagpur. The author has contributed to research in topics: Field-programmable gate array & Very-large-scale integration. The author has an hindex of 18, co-authored 146 publications receiving 1230 citations. Previous affiliations of Anindya Sundar Dhar include Indian Institutes of Technology.

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CORDIC architectures: a survey

TL;DR: This paper presents systematic and comprehensive taxonomy of rotational CORDIC algorithms, and detailed comparison of various algorithms is presented, which can provide a first-order information to designers looking for either further improvement of performance or selection of rotations for a specific application.
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Optical properties of CdS nanowires prepared by dc electrochemical deposition in porous alumina template

TL;DR: In this article, the growth of Cadmium sulfide (CdS) nanowires on porous alumina template has been investigated using dc electrochemical method, and the micro-structural study of the CdS nano-structures has been carried out using atomic force microscopy, field-emission scanning electron microscopy and transmission electron microscope.
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Charge storage and photoluminescence characteristics of silicon oxide embedded Ge nanocrystal trilayer structures

TL;DR: In this paper, a trilayer structure consisting of the cap gate oxide, sputtered SiGe layers and thermally grown tunnel oxide was fabricated on p-Si substrates.
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FPGA realization of a CORDIC based FFT processor for biomedical signal processing

TL;DR: The processor is implemented in a field programmable gate array (FPGA) that is a very cost effective option for low design cycle desktop testing, and its performance is found to be satisfactory.
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Nonvolatile Memristive Switching Characteristics of TiO $_{\bm 2}$ Films Embedded With Nickel Nanocrystals

TL;DR: The role of thin Ni-NC layer on memory switching stability is discussed in this article, where stable, bipolar, nonvolatile, and bistable resistive switching states are observed for the optimized annealed NiNC-embedded devices with a low SET and RESET voltage of 0.8 and -0.2 V, respectively.