Showing papers by "Saibal Mukhopadhyay published in 2012"
TL;DR: In this article, the potential of using multiple TECs for hot spot cooling to obtain favorable thermal profile on chip in an energy efficient way was analyzed, and the authors showed that the effect of TEC coupling on transient cooling is weak.
Abstract: Site-specific on-demand cooling of hot spots in microprocessors can reduce peak temperature and achieve a more uniform thermal profile on chip, thereby improve chip performance and increase the processor’s life time An array of thermoelectric coolers (TECs) integrated inside an electronic package has the potential to provide such efficient cooling of hot spots on chip This paper analyzes the potential of using multiple TECs for hot spot cooling to obtain favorable thermal profile on chip in an energy efficient way Our computational analysis of an electronic package with multiple TECs shows a strong conductive coupling among active TECs during steady-state operation Transient operation of TECs is capable of driving cold-side temperatures below steady-state values Our analysis on TEC arrays using current pulses shows that the effect of TEC coupling on transient cooling is weak Various pulse profiles have been studied to illustrate the effect of shape of current pulse on the operation of TECs considering crucial parameters such as total energy consumed in TECs peak temperature on the chip, temperature overshoot at the hot spot and settling time during pulsed cooling of hot spots The square root pulse profile is found to be the most effective with maximum cooling and at half the energy expenditure in comparison to a constant current pulse We analyze the operation of multiple TECs for cooling spatiotemporally varying hot spots The analysis shows that the transient cooling using high amplitude current pulses is beneficial for short term infrequent hot spots, but high amplitude current pulse cannot be used for very frequent or long lasting hot spots
33 citations
TL;DR: An all-digital technique to modulate the system clock and local clocks in response to global and local voltage noise to prevent timing errors during low-voltage operation is presented.
Abstract: This paper presents an all-digital technique to modulate the system clock and local clocks in response to global and local voltage noise to prevent timing errors during low-voltage operation. The critical path replica circuits are utilized to change the clock period within a clock cycle in response to transient supply noise. Measurement in 130-nm CMOS demonstrates reliable operation of a test pipeline over a wide dc (1.3-0.74 V) voltage range. At 0.81 V, the pipeline operates without timing errors at 7.2% higher frequency even under a 189-mV transient voltage droop.
20 citations
09 Mar 2012
TL;DR: The control principles for TEC assisted transient cooling are presented and their impact on reducing thermal violations in microprocessors and TEC energy dissipations are discussed.
Abstract: Super-lattice thin-film thermoelectric coolers (TEC) are emerging as a promising technology for hot spot mitigation in microprocessors. This paper studies the prospect of on-demand cooling with advanced TECs integrated at the back of the heat spreader inside a package (integrated TEC). The thermal compact models of the chip and package with integrated TECs are developed and used for steady-state and transient temperature analysis. The control principles for TEC assisted transient cooling are presented and their impact on reducing thermal violations in microprocessors and TEC energy dissipations are discussed.
16 citations
TL;DR: For a given migration frequency, global coolest replace policy is found to be the most effective among the three policies considered as this policy provides 10 °C reduction in peak temperature and 20 °C reduce in maximum spatial temperature difference on a 256 core chip.
Abstract: In this paper, a proactive thermal management technique called “power multiplexing” is explored for many-core processors. Power multiplexing involves redistribution of the locations of active cores at regular time intervals to obtain uniform thermal profile with low peak temperature. Three different migration policies namely random, cyclic, and global coolest replace have been employed for power multiplexing and their efficacy in reducing the peak temperature and thermal gradient on chip is investigated. For a given migration frequency, global coolest replace policy is found to be the most effective among the three policies considered as this policy provides 10 °C reduction in peak temperature and 20 °C reduction in maximum spatial temperature difference on a 256 core chip. Power configuration on the chip is characterized by a parameter called “proximity index” which emerges as an important parameter to represent the spatial power distribution on a chip. We also notice that the overall performance of the chip could be improved by 10% using global multiplexing.
13 citations
15 Oct 2012
TL;DR: Measurements from a 130nm test-chip show that the Zero-Temperature-Coefficient (ZTC) point varies by circuit type, and further fluctuates due to process variation, and a more accurate ITD-sensitive thermal sensor is thus needed for better temperature tracking.
Abstract: As the supply voltage (V DD ) approaches the device threshold voltage (V T ), the elevated temperature results in increased device current. This phenomenon is generally known as Inverse Temperature Dependence (ITD). In this paper, we propose a test structure with a built-in poly-resistor-based heater to characterize ITD in digital circuits. Our measurements from a 130nm test-chip show that the Zero-Temperature-Coefficient (ZTC) point varies by circuit type, and further fluctuates due to process variation. A more accurate ITD-sensitive thermal sensor is thus needed for better temperature tracking.
13 citations
09 Mar 2012
TL;DR: The overall TAVS architecture is presented and the circuit issues associated with design of 3D level shifters are discussed and the possibility of 26%-39% reduction in chip delay distribution is shown.
Abstract: This paper presents tier-adaptive-voltage-scaling (TAVS) as a post-silicon tuning methodology for improving parametric yield of 3D integrated circuits considering die-to-die and within-die process variations. The TAVS methodology senses process corners of individual tiers using on-tier delay sensors and adapt the supply voltage of each tier. The overall TAVS architecture is presented and the circuit issues associated with design of 3D level shifters are discussed. Circuit level simulation and statistical analysis of the TAVS architecture in predictive 45nm technology show the possibility of 26%–39% reduction in chip delay distribution.
12 citations
18 Mar 2012
TL;DR: A methodology for post-silicon thermal prediction to predict the transient thermal field a multicore package for various workload considering chip-to-chip variations in electrical and thermal properties is presented.
Abstract: This paper presents a methodology for post-silicon thermal prediction to predict the transient thermal field a multicore package for various workload considering chip-to-chip variations in electrical and thermal properties. We use time-frequency duality to represent thermal system in frequency domain as a low-pass filter augmented with a positive feedback path for leakage-temperature interaction. This thermal system is identified through power/thermal measurements on a packaged IC and is used for post-silicon thermal prediction. The effectiveness of the proposed effort is presented considering a 64 core processor in predictive 22nm node and SPEC2006 benchmark applications.
10 citations
18 Mar 2012
TL;DR: In this article, the thermal coupling in a 3D stack with multiple cores in one tier and an SRAM array (cache) in a second tier with face-to-back bonding was studied using 32nm predictive technology.
Abstract: We study the thermal coupling in a 3D stack with multiple cores in one tier and an SRAM array (cache) in a second tier with face-to-back bonding. For identical statistical distribution of power dissipation in cores, the SRAM sub-arrays experience much higher mean and variance in temperature in a 3D stack compared to a conventional 2D system. The increased variability in temperature increases leakage, degrades performance, and accelerates aging in 3D integrated SRAM. This is studied using 32nm predictive technology. Further, the spatial and temporal variations in performance of SRAM blocks become a strong function of the power variations in cores.
8 citations
19 Mar 2012
TL;DR: An instruction-based energy estimation model for fast and scalable energy simulation, where the dynamic energy is modeled as a combination of three contributing factors: physical, microarchitectural, and workload properties.
Abstract: Processor power is a complex function of device, packaging, microarchitecture, and application. Typical approaches to power simulation require detailed microarchitecture models to collect the statistical switching activity counts of processor components. In manycore simulations, the detailed core models are the main simulation speed bottleneck. In this paper, we propose an instruction-based energy estimation model for fast and scalable energy simulation. Importantly, in this approach the dynamic energy is modeled as a combination of three contributing factors: physical, microarchitectural, and workload properties. The model easily incorporates variations in physical parameters such as clock frequencies and supply voltages. When compared to commonly used cycle-level microarchitectural simulation approach with SPEC2006 benchmarks, the proposed instruction-based energy model incurred a 2.94% average error rate while achieving an average simulation time speedup of 74X for a 16-core asymmetric x86 ISA processor model with multiple clock domains operating at different frequencies.
8 citations
TL;DR: A case report of a fifty-year-old woman who was receiving empirical anti-tubercular drugs for a metastatic illness to lungs arising from a primary angiosarcoma in the right atrium is described.
Abstract: In Indian settings pulmonary tuberculosis remains the most common diagnosis in a patient presenting with constitutional symptoms, hemoptysis and lung opacities. We describe a case report of a fifty-year-old woman who was receiving empirical anti-tubercular drugs for a metastatic illness to lungs arising from a primary angiosarcoma in the right atrium. This rare entity was misdiagnosed and typical echocardiographic findings suggested this diagnosis.
7 citations
Patent•
IBM1
TL;DR: In this paper, the results of forward simulations of circuit yield, the results including at least circuit yield results including simulated device shapes, are used to determine high-level traits of at least the device shapes.
Abstract: Techniques are presented that include accessing results of forward simulations of circuit yield, the results including at least circuit yield results including simulated device shapes. Using the circuit yield results, high-level traits of at least the simulated device shapes are determined. Based on the determined high-level traits and using the circuit yield results, a compact model for predicted yield is constructed, the compact model including a plurality of adjustable parameters, and the constructing the compact model for predicted yield including adjusting the adjustable parameters until at least one first predetermined criterion is met. An optimization problem is constructed including at least the compact model for yield, an objective, and a plurality of constraints. Using the optimization problem, the objective is modified subject to the plurality of constraints until at least one second predetermined criterion is met.
TL;DR: It is reported successful reversion of polymorphic ventricular tachycardia secondary to amiodarone toxicity by phenytoin administration that was resistant to the conventional drugs (magnesium sulphate, lidocaine and atropine).
Abstract: Phenytoin, a class IB anti-arrhythmic agent, is considered the drug of choice for ventricular arrhythmias due to digoxin toxicity. We report successful reversion of polymorphic ventricular tachycardia secondary to amiodarone toxicity by phenytoin administration that was resistant to the conventional drugs (magnesium sulphate, lidocaine and atropine).
23 Apr 2012
TL;DR: A test circuit is presented for post-silicon and on-line characterization of the energy-inflection activity of power-gated circuits under static and dynamic variations.
Abstract: A test circuit is presented for post-silicon and on-line characterization of the energy-inflection activity of power-gated circuits (the activity when overhead energy is equal to leakage savings) under static (process) and dynamic (voltage/temperature/input) variations. The test circuit is applied to design self-adaptive power-gating for energy-efficient SRAM.
23 Apr 2012
TL;DR: This paper analyzes the supply crosstalk between logic cores and SRAMs on separate tiers in a 3D die-stack using a distributed RLC based 3D power grid model and shows that due to the supply cross-talk power variation in cores modulates the performances and parametric failures in SRAM.
Abstract: This paper analyzes the supply crosstalk between logic cores and SRAMs on separate tiers in a 3D die-stack using a distributed RLC based 3D power grid model. The analysis shows that due to the supply cross-talk power variation in cores modulates the performances and parametric failures in SRAM.
TL;DR: This article presents a design methodology for accuracy aware, energy efficient wireless monitoring of electroencephalography (EEG) data that performs a real-time accuracy energy trade-off by controlling the volume of transmitted data based on the information content in the EEG signal.
Abstract: Remote wireless monitoring of physiological signals has emerged as a key enabler for biotelemetry and can significantly improve the delivery of healthcare. Improving the energy efficiency and battery lifetime of the monitoring units without sacrificing the acquired signal quality is a key challenge in large-scale deployment of bioelectronic systems for remote wireless monitoring. In this article, we present a design methodology for accuracy aware, energy efficient wireless monitoring of electroencephalography (EEG) data. The proposed design performs a real-time accuracy energy trade-off by controlling the volume of transmitted data based on the information content in the EEG signal. We consider the effect of different system parameters in order to design an optimal system. We analyze the impact of noise of the wireless channel. Our analysis shows that the proposed system design approach can provide up to 10X energy savings in a 32 channel wireless EEG system with minimal impact on the monitored EEG signal accuracy.
10 Apr 2012
TL;DR: For logic circuits, timing error prevention using time-borrowing and clock stretching is discussed as a feasible approach to reduce power dissipation for a target throughput.
Abstract: This paper presents error tolerance and error prevention methodologies to reduce power dissipation in digital circuits under process variations. For logic circuits, timing error prevention using time-borrowing and clock stretching is discussed as a feasible approach to reduce power dissipation for a target throughput. The natural error tolerance in image processing applications is exploited to reduce power dissipations in Static Random Access Memory (SRAM).