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Sanjit Kumar Swain

Researcher at Silicon Institute of Technology

Publications -  48
Citations -  283

Sanjit Kumar Swain is an academic researcher from Silicon Institute of Technology. The author has contributed to research in topics: MOSFET & Transconductance. The author has an hindex of 8, co-authored 46 publications receiving 183 citations. Previous affiliations of Sanjit Kumar Swain include Sambalpur University & Indian Institute of Technology Dhanbad.

Papers
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Influence of channel length and high-K oxide thickness on subthreshold analog/RF performance of graded channel and gate stack DG-MOSFETs

TL;DR: The results validate that variations in t oxh of the device significantly alters device performance parameters and must be pre accounted for realizing reliable analog/RF system on chip circuits.
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High performance AlInN/AlN/GaN p-GaN back barrier Gate-Recessed Enhancement-Mode HEMT

TL;DR: In this paper, the authors proposed and performed extensive simulation study of the novel device structure having a p-GaN back barrier layer inserted in the conventional AlInN/AlN/GaN Gate-Recessed Enhancement-Mode HEMT device for reducing the short channel effects, gate leakage and enhancing the frequency performance.
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Isotope (C and O) composition of auriferous quartz carbonate veins, central lode system, Gadag Gold Field, Dharwar Craton, India: Implications to source of ore fluids

TL;DR: Sarma et al. as discussed by the authors examined the carbon and oxygen isotope compositions of auriferous quartz-carbonate veins of gold deposits from Sangli, Kabuliyatkatti, Nagavi, Nabapur and Mysore mining areas developed on the Central Lode system of the Gadag Gold Field (GGF) in the Neoarchaean Gadag schist belt of the Dharwar Craton, southern India.
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Study of HfAlO/AlGaN/GaN MOS-HEMT with source field plate structure for improved breakdown voltage

TL;DR: In this article, a source field-plated AlGaN/GaN in the metal oxide Semiconductor high electron mobility transistors (MOS-HEMT) structure having a relatively short gate length and short gate-to-drain distances is analyzed.
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Impact of InGaN back barrier layer on performance of AIInN/AlN/GaN MOS-HEMTs

TL;DR: In this article, the effect of InGaN back barrier on device performances of 100nm gate length AlInN/AlN/GaN metal oxide semiconductor high electron mobility transistor (MOS-HEMT) device and a wide comparison is made with respect to without considering the back barrier layer.