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Seokhyeong Kang
Researcher at Pohang University of Science and Technology
Publications - 93
Citations - 1379
Seokhyeong Kang is an academic researcher from Pohang University of Science and Technology. The author has contributed to research in topics: Computer science & Ternary operation. The author has an hindex of 15, co-authored 74 publications receiving 1095 citations. Previous affiliations of Seokhyeong Kang include Samsung & University of California.
Papers
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Proceedings ArticleDOI
Accuracy-configurable adder for approximate arithmetic designs
Andrew B. Kahng,Seokhyeong Kang +1 more
TL;DR: This paper proposes an accuracy-configurable approximate adder for which the accuracy of results is configurable during runtime, and can be used in accuracy- configurable applications, and improves the achievable tradeoff between performance/power and quality.
Proceedings ArticleDOI
Slack redistribution for graceful degradation under voltage overscaling
TL;DR: This work proposes a design-level approach to trading off reliability and voltage (power) in, e.g., microprocessor designs through techniques for power-aware slack redistribution that shift the timing slack of frequently-exercised, near-critical timing paths in a power- and area-efficient manner.
Proceedings ArticleDOI
Designing a processor from the ground up to allow voltage/reliability tradeoffs
TL;DR: In this paper, the authors present a power-aware slack redistribution technique to increase the range of voltages over which the incidence of operational (timing) errors is acceptable for soft architectures.
Proceedings ArticleDOI
Sensitivity-guided metaheuristics for accurate discrete gate sizing
TL;DR: A metaheuristic approach to gate sizing that integrates timing and power optimization, and handles several types of constraints is developed that outperforms the best-reported results on all but one of the ISPD 2012 benchmarks.
Journal ArticleDOI
A Logic Synthesis Methodology for Low-Power Ternary Logic Circuits
TL;DR: The proposed ternary full adder has a significant improvement in the power-delay product (PDP) over previous designs and is applicable to both unbalanced (0, 1, 2) and balanced (−1, 0, 1) ternARY logic.