Showing papers in "IEEE Transactions on Circuits and Systems I-regular Papers in 2020"

Semi-Supervised Broad Learning System Based on Manifold Regularization and Broad Network

Abstract: Broad Learning System (BLS) are widely used in many fields because of its strong feature extraction ability and high computational efficiency. However, the BLS is mainly used in supervised learning, which greatly limits the applicability of the BLS. And the obtained data is less labeled data, but is a large number of unlabeled data. Therefore, the BLS is extended based on the semi-supervised learning of manifold regularization framework to propose a semi-supervised broad learning system (SS-BLS). Firstly, the features are extracted from labeled and unlabeled data by building feature nodes and enhancement nodes. Then the manifold regularization framework is used to construct Laplacian matrix. Next, the feature nodes, enhancement nodes and Laplacian matrix are combined to construct the objective function, which is effectively solved by ridge regression in order to obtain the output coefficients. Finally, the validity of the SS-BLS is verified by three different complex data of G50C, MNIST, and NORB, respectively. The experiment result show that the SS-BLS can achieve higher classification accuracy for different complex data, takes on fast operation speed and strong generalization ability.

Comparison and Extension of Approximate 4-2 Compressors for Low-Power Approximate Multipliers

Abstract: Approximate multipliers attract a large interest in the scientific literature that proposes several circuits built with approximate 4-2 compressors. Due to the large number of proposed solutions, the designer who wishes to use an approximate 4-2 compressor is faced with the problem of selecting the right topology. In this paper, we present a comprehensive survey and comparison of approximate 4-2 compressors previously proposed in literature. We present also a novel approximate compressor, so that a total of twelve different approximate 4-2 compressors are analyzed. The investigated circuits are employed to design $8\times 8$ and $16\times 16$ multipliers, implemented in 28nm CMOS technology. For each operand size we analyze two multiplier configurations, with different levels of approximations, both signed and unsigned. Our study highlights that there is no unique winning approximate compressor topology since the best solution depends on the required precision, on the signedness of the multiplier and on the considered error metric.

Observer-Based Asynchronous Fault Detection for Conic-Type Nonlinear Jumping Systems and its Application to Separately Excited DC Motor

Abstract: This work investigates the observer-based asynchronous fault detection problem for a class of nonlinear Markov jumping systems. The conic-type nonlinearities hold such a restrictive condition that locates in a known hypersphere with an undefined centre. In order to guarantee the observer modes run synchronously with the system modes, we introduce a hidden Markov model to deal with this difficulty. Utilizing $H_\infty $ and $H_\_{}$ performance index, a multi-targets strategy of asynchronous fault detection problem is formulated. Via linear matrix inequality, sufficient conditions for the presence of the asynchronous fault detection observer are derived respectively. Then an asynchronous fault detection algorithm is formulated. Finally, the application of dynamic equivalent circuit of separately excited DC motor with three cases is employed to illustrate that the devised asynchronous fault detection observer is able to detect the faults after the appearances in the absence of any incorrect alarm.

Attack-Resilient Event-Triggered Controller Design of DC Microgrids Under DoS Attacks

Abstract: This paper is concerned with the attack-resilient event-triggered controller design problem of a DC microgrid with multiple nonlinear constant power loads and intermittent denial-of-service (DoS) attacks. First, for a resource efficiency purpose, an event-triggering communication scheme is delicately devised in such a way to only invoke the data transmission over the communication line when the DoS attack is inactive. Second, via characterizing the DoS active and inactive time intervals, a new switching piecewise system model for the nonlinear DC microgrid system is presented. Third, a numerically efficient design criterion on the existence of the desired attack-resilient event-triggered controller is established. It is further shown that various performance indices including resource efficiency, attack resilience, robustness against disturbance, sampling performance of the DC microgrid system can be evaluated in a unified framework. Finally, an illustrative example is given to verify the effectiveness of the proposed control design method for the DC microgrid.

Energy-Constraint Formation for Multiagent Systems With Switching Interaction Topologies

Abstract: The current paper investigates energy-constraint formation design and analysis problems for multiagent systems with two types of switching interaction topologies; that is, leaderless ones and leader-following ones. Firstly, a new formation control protocol with switching interaction topologies is shown, where the whole energy supply is limited previously. Then, by constructing the relationship of the whole energy supply and the matrix variable, sufficient conditions for leaderless energy-constraint formation design and analysis are respectively presented by the linear matrix inequality tool. Furthermore, an approach is proposed to determine an explicit expression of the formation center function, which determines the macroscopic motion of a multiagent system as a whole and consists of two parts: the initial state term and the formation function term. Moreover, main conclusions of leaderless energy-constraint formation are extended into leader-following multiagent systems by a new two-step transformation approach, where the asymmetric structure feature of leader-following switching interaction topologies is well dealt with. Finally, two numerical examples are provided to demonstrate the effectiveness of main conclusions.

In-Memory Low-Cost Bit-Serial Addition Using Commodity DRAM Technology

Abstract: In-memory computing architectures present a promising solution to address the memory- and the power-wall challenges by mitigating the bottleneck between processing units and storage. Such architectures incorporate computing functionalities inside memory arrays to make better use of the large internal memory bandwidth, thereby, avoiding frequent data movements. In-DRAM computing architectures offer high throughput and energy improvements in accelerating modern data-intensive applications like machine learning etc . In this manuscript, we propose a vector addition methodology inside DRAM arrays through functional read enabled on local word-lines. The proposed primitive performs majority-based addition operations by storing data in transposed manner. Majority functions are achieved in DRAM cells by activating odd number of rows simultaneously. The proposed majority based bit-serial addition enables huge parallelism and high throughput. We validate the robustness of the proposed in-DRAM computing methodology under process variations to ascertain its reliability. Energy evaluation of the proposed scheme shows 21.7X improvement compared to normal data read operations in standard DDR3-1333 interface. Moreover, compared to state-of-the-art in-DRAM compute proposals, the proposed scheme provides one of the fastest addition mechanisms with low area overhead ( ${k}$ -Nearest Neighbor ( ${k}$ NN) algorithm on the MNIST handwritten digit classification dataset shows 11.5X performance improvement compared to a conventional von-Neumann machine.

An Adaptive SOSM Controller Design by Using a Sliding-Mode-Based Filter and its Application to Buck Converter

Abstract: In this paper, a novel adaptive second-order sliding mode (SOSM) control method is proposed by combining a new adaptive strategy with the backstepping-like technique. The new adaptive strategy is first constructed by means of the equivalent control for which a sliding-mode-based filter is employed rather than the widely-used low-pass filter such that the parameter restriction under the usage of low-pass filter can be relaxed. Then, by applying the proposed adaptive strategy and the idea of adding a power integrator, an adaptive SOSM method is established to finite-time stabilize the sliding variables. The feature of the proposed SOSM method lies in that the gain will vary with the size of the lumped uncertainty so as to avoid the overestimation of the gain. The stability analysis is given based on the finite-time Lyapunov theory. The theoretical results are finally applied to the voltage regulation problem of a Buck converter.

Finite-Time $H_{\infty}$ Filtering for State-Dependent Uncertain Systems With Event-Triggered Mechanism and Multiple Attacks

Abstract: This paper is concerned with finite-time $H_{\infty }$ filtering problem for networked state-dependent uncertain systems with event-triggered mechanism and multiple attacks, which consists of deception attacks, denial-of-service (DoS) attacks and replay attacks. A novel multiple attacks model is firstly proposed for state-dependant uncertain systems with consideration of the randomly occurring replay attacks, DoS attacks and deception attacks in a unified framework. In order to save the limited resource, an event-triggered mechanism is used to ease the communication burden in real communication environment. Then, by using Lyapunov-Krasocskii stability theory and linear matrix inequality techniques, sufficient conditions guaranteeing the exponentially mean-square finite-time boundedness of filtering error systems are obtained. Moreover, the explicit expression is derived for the parameters of the desired finite-time filter. Finally, two illustrative examples are employed to demonstrate the validity and applicability of the proposed theoretical approach in electronic circuits.

A Logic Synthesis Methodology for Low-Power Ternary Logic Circuits

Abstract: We propose a logic synthesis methodology with a novel low-power circuit structure for ternary logic. The proposed methodology synthesizes a ternary function as a ternary logic gate using carbon nanotube field-effect transistors (CNTFETs). The circuit structure uses the body effect to mitigate the excessive power consumption for the third logic value. Energy-efficient ternary logic circuits are designed with a combination of synthesized low-power ternary logic gates. The proposed methodology is applicable to both unbalanced (0, 1, 2) and balanced (−1, 0, 1) ternary logic. To verify the improvement in energy efficiency, we have designed various ternary arithmetic logic circuits using the proposed methodology. The proposed ternary full adder has a significant improvement in the power-delay product (PDP) over previous designs. Ternary benchmark circuits have been designed to show that complex ternary functions can be designed to more efficient circuits with the proposed methodology.

Comprehensive Conception of High Step-Up DC–DC Converters With Coupled Inductor and Voltage Multipliers Techniques

Abstract: Due to the plethora of non-isolated high gain step-up dc-dc converters presented in the literature, it has become important to comprehensively review and classify them, as well as to derive methods to generalize the usage of the commonly employed techniques. Motivated by this need, this paper not only proposes a new family of high gain step up dc-dc converter, but a generalized methodology to derive them from any classical dc-dc topology by applying a coupled inductor and voltage multiplier cells. For illustrating the methodology, high gain dc-dc converters based on the basic topologies (Buck, Boost, and Buck-Boost) are developed and analyzed. These converters are compared in terms of voltage gain, coupled inductor size, voltage stresses, total device rating, switching frequency effect in power loss, and output power regulation. Moreover, in order to verify the proposal, two practical experimentations are accomplished. Firstly, a prototype able to operate as any of the three basic topologies with different gain cells is developed for comparing theoretical, simulated, and experimental static gain results. Secondly, well-designed prototypes concerning to the Buck-, Boost-, and Buck-Boost-based converters are assembled for efficiency evaluation.

VPQC: A Domain-Specific Vector Processor for Post-Quantum Cryptography Based on RISC-V Architecture

Abstract: In the 5G era, massive devices need to be securely connected to the edge of communication networks, while emerging quantum computers can easily crack the traditional public-key ciphers. Lattice-based cryptography (LBC) is one of the most promising types of schemes in all post-quantum cryptography (PQC) due to its security and efficiency. To meet the requirements of high-throughput and diverse application scenarios of 5G, we investigate the vectorization of kernel algorithms of several LBC candidates and thus present a domain-specific vector processor, VPQC, leveraging the extensible RISC-V architecture. To support the parallel computation of number theoretic transform (NTT) of different dimensions (from 64 to 2048), a vector NTT unit is implemented in VPQC. Besides, a vector sampler executing both uniform sampling and binomial sampling is also employed. Evaluated under TSMC 28nm technology, the vector coprocessor of VPQC consumes 942k equivalent logic gates and 12KB memories. Experimental results show that VPQC can speed up several typical key encapsulation mechanisms (NewHope, Kyber and LAC) by an order of magnitude compared with previous state-of-the-art hardware implementations.

Periodic Event-Triggered Adaptive Control for Attitude Stabilization Under Input Saturation

Abstract: In the paper, the periodic event-triggered adaptive controller is proposed for attitude stabilization of a rigid spacecraft with model uncertainties, external disturbances, and input saturation. We adopt the periodic state measurement instead of the continuous one, and it is known that the former is more economical and practical than the latter due to the relaxation of continuous measurements. Moreover, new event-triggered adaptation update laws and the periodic event-triggering strategy are proposed for adaptive sliding mode control (SMC) to guarantee the states in the practical sliding mode. It is illustrated that the states of the attitude control system are ultimately bounded. Further, it is proved that the presented periodic event-triggered strategy is without $Zeno$ phenomenon and there exists a uniform lower bound for each interevent time. Some numerical examples are given to demonstrate the validity of the derived control strategy.

Unified Stability Criteria of Random Nonlinear Time-Varying Impulsive Switched Systems

Abstract: This paper investigates the problem of noise-to-state practical stability in mean (NSpS-M) (which is a natural generalization of noise-to-state stability in mean) and the problem of almost sure global asymptotic stability (GAS a.s.) for a class of random nonlinear time-varying impulsive switched systems. By using the notions of average impulsive switched interval and Poisson process, unified sufficient stability criteria on NSpS-M and GAS a.s. are derived. Two remarkable distinctions from the existing results lie in that: (1) stabilizing, inactive and destabilizing impulses are simultaneously considered; (2) the coefficient of the derivative of a Lyapunov function is allowed to be a time-varying function which can be both positive and negative and may even be unbounded. As an accompaniment, a less conservative unified criterion on NSpS-M for a special case is also presented by taking into account the stabilization role of the gain constant of the time-varying coefficient. Two examples are provided to illustrate the effectiveness of our derived criteria.

Optimizing Weight Mapping and Data Flow for Convolutional Neural Networks on Processing-in-Memory Architectures

Abstract: Recent state-of-the-art deep convolutional neural networks (CNNs) have shown remarkable success in current intelligent systems for various tasks, such as image/speech recognition and classification. A number of recent efforts have attempted to design custom inference engines based on processing-in-memory (PIM) architecture, where the memory array is used for weighted sum computation, thereby avoiding the frequent data transfer between buffers and computation units. Prior PIM designs typically unroll each 3D kernel of the convolutional layers into a vertical column of a large weight matrix, where the input data needs to be accessed multiple times. In this paper, in order to maximize both weight and input data reuse for PIM architecture, we propose a novel weight mapping method and the corresponding data flow which divides the kernels and assign the input data into different processing-elements (PEs) according to their spatial locations. As a case study, resistive random access memory (RRAM) based 8-bit PIM design at 32 nm is benchmarked. The proposed mapping method and data flow yields $\sim 2.03\times $ speed up and $\sim 1.4\times $ improvement in throughput and energy efficiency for ResNet-34, compared with the prior design based on the conventional mapping method. To further optimize the hardware performance and throughput, we propose an optimal pipeline architecture, with ~50% area overhead, it achieves overall $913\times $ and $1.96\times $ improvement in throughput and energy efficiency, which are 132476 FPS and 20.1 TOPS/W, respectively.

Discrete-Communication-Based Bipartite Tracking of Networked Robotic Systems via Hierarchical Hybrid Control

Abstract: This paper investigates the bipartite tracking problem of networked robotic systems (NRSs) subject to input disturbances, discrete communications and signed directed graphs. Two new classes of hierarchical hybrid control algorithms (HHCAs), which involve both continuous and discontinuous signals in a uniform framework, are designed to solve the aforementioned problem in the model-independent control manner, i.e., without using the prior information of the system model. Besides, with the help of the Lyapunov statement and hybrid system theory, we establish several sufficient conditions for guaranteeing the convergence of the proposed hybrid algorithms. Finally, numerical examples are presented to illustrate the effectiveness of the proposed results.

One-Sided Schmitt-Trigger-Based 9T SRAM Cell for Near-Threshold Operation

Abstract: This paper presents a one-sided Schmitt-trigger-based 9T static random access memory cell with low energy consumption and high read stability, write ability, and hold stability yields in a bit-interleaving structure without write-back scheme. The proposed Schmitt-trigger-based 9T static random access memory cell obtains a high read stability yield by using a one-sided Schmitt-trigger inverter with a single bit-line structure. In addition, the write ability yield is improved by applying selective power gating and a Schmitt-trigger inverter write assist technique that controls the trip voltage of the Schmitt-trigger inverter. The proposed Schmitt-trigger-based 9T static random access memory cell has 0.79, 0.77, and 0.79 times the area, and consumes 0.31, 0.68, and 0.90 times the energy of Chang's 10T, the Schmitt-trigger-based 10T, and MH's 9T static random access memory cells, respectively, based on 22-nm FinFET technology.

IMAC: In-Memory Multi-Bit Multiplication and ACcumulation in 6T SRAM Array

Abstract: ‘In-memory computing’ is being widely explored as a novel computing paradigm to mitigate the well known memory bottleneck. This emerging paradigm aims at embedding some aspects of computations inside the memory array, thereby avoiding frequent and expensive movement of data between the compute unit and the storage memory. In-memory computing with respect to Silicon memories has been widely explored on various memory bit-cells. Embedding computation inside the 6 transistor (6T) SRAM array is of special interest since it is the most widely used on-chip memory. In this paper, we present a novel in-memory multiplication followed by accumulation operation capable of performing parallel dot products within 6T SRAM without any changes to the standard bitcell. We, further, study the effect of circuit non-idealities and process variations on the accuracy of the LeNet-5 and VGG neural network architectures against the MNIST and CIFAR-10 datasets, respectively. The proposed in-memory dot-product mechanism achieves 88.8% and 99% accuracy for the CIFAR-10 and MNIST, respectively. Compared to the standard von Neumann system, the proposed system is $6.24\times $ better in energy consumption and $9.42\times $ better in delay.

Theoretical Foundations of Memristor Cellular Nonlinear Networks: Memcomputing With Bistable-Like Memristors

Abstract: This paper presents the theory of a novel memcomputing paradigm based upon a memristive version of standard Cellular Nonlinear Networks. The insertion of a nonvolatile memristor in the circuit of each cell endows the dynamic array with the capability to store and retrieve data into and from the resistance switching memories, obviating the current need for extra memory blocks. Choosing the parameters of each cell circuit so that the memristors may undergo solely sharp transitions between two states, each processing element may be approximately described at any time as one of two first-order systems. Under this assumption, the classical Dynamic Route Map may be employed to synthesise and analyse the data storage and retrieval genes. A new system-theoretic methodology, called Second-Order Dynamic Route Map , is also introduced for the first time in this paper. This technique allows to study the operating principles of arrays with second-order processing elements, as is the case, in the proposed network, if the set up of cell circuit parameters induces analogue memristive dynamics. This paper shows how the novel tool may be adopted to investigate the operating mechanisms of a cellular array with second-order cells, which compute the element-wise logical OR between two binary images.

Bandwidth Enhancement of Doherty Power Amplifier Using Modified Load Modulation Network

Abstract: A novel Doherty power amplifier (DPA) architecture with extended bandwidth is presented in this paper. A modified load modulation network is introduced to provide impedance condition required by the Doherty operation in a wide frequency range. Analytical parameter solutions of the proposed load modulation network and the related load modulation process are presented. A DPA with 2.80-3.55 GHz bandwidth utilizing commercial GaN transistors is implemented. The fabricated DPA attains a measured 9.3-11.1 gain and 43.0-45.0 dBm saturated power. 50.0-60.6% and 66-78% drain efficiency is obtained at 6 dB output power back-off and saturation throughout the designed band, respectively. Moreover, the back-off drain efficiencies are higher than 55% within 700 MHz bandwidth. When driven by a 6-carrier 120 MHz OFDM signal with 7.0 dB peak to average power ratio, the proposed DPA achieves adjacent channel leakage ratio of better than −50 dBc after digital pre-distortion (DPD) at 3.20 GHz with average efficiency of 53.3%.

A Novel Approach to State and Unknown Input Estimation for Takagi–Sugeno Fuzzy Models With Applications to Fault Detection

Abstract: In this paper, a novel approach is proposed for state and unknown input estimation of Takagi-Sugeno fuzzy systems. By introducing an augmented state vector, containing both system state and the unknown input, a functional observer is proposed to estimate this vector, and the proposed observer provides a highly flexible estimation output. Through casting the observer design problem into an equivalent solvability problem of a linear matrix equation with respect to the observer gains, the existence condition for the proposed observer is explicitly derived in terms of matrix rank. Furthermore, a parameterization methodology of the observer gain matrices is provided as well, which avoids directly solving the Sylvester equation. The proposed observer design scheme is further applied to the $H\_{}/H_\infty $ fault detection problem, and the effectiveness of the proposed approach is demonstrated by state and unknown input estimation for a tunnel diode circuit and fault detection for a continuously stirred tank reactor system.

Theoretical Foundations of Memristor Cellular Nonlinear Networks: Stability Analysis With Dynamic Memristors

Abstract: If the memristor, used in each cell of a memristive variant of the standard space-invariant Cellular Nonlinear Network (CNN), undergoes analogue memductance changes, the processing element operates as a second-order system. The Dynamic Route Map (DRM) technique, applicable to investigate first-order systems only, is no longer relevant. In this manuscript, a recently introduced methodology, generalizing the DRM technique to second-order systems, is applied to the models of Memristor CNN (M-CNN) cells, accomodating dynamic memristors. This allows to gain insights into the operating principles of these cellular structures, which make computations through the evolution of their states toward prescribed equilibria. Our analysis uncovers all possible local and global phenomena, which may emerge in the cell phase space under zero offset current for any self-feedback synaptic weight. Under these hypotheses, the dynamics of the M-CNN cell may significantly differ from those of a standard space-invariant CNN counterpart. The insertion of an offset current into each cell endows it with further properties, including monostability. The analysis method is used to demonstrate how a non-autonomous memristive array exploits the capability of its cells to feature monostability or bistability, depending upon the respective offset currents, to compute the element-wise logical AND between two binary images.

Theoretical Foundations of Memristor Cellular Nonlinear Networks: A DRM 2 -Based Method to Design Memcomputers With Dynamic Memristors

Abstract: In the memristive version of a standard space-invariant Cellular Nonlinear Network, each cell accommodates one first-order non-volatile memristor in parallel with a capacitor. In case, the resistance switching memory may only undergo almost-instantaneous switching transitions between two possible resistive states, acting at any time, as either the on or the off resistor, the processing elements effectively operate as first-order dynamical systems, and the classical Dynamic Route Map technique may be applied to investigate their operating principles. On the contrary, in case the memristors experience smooth conductance changes, as the bioinspired array implements memcomputing paradigms, each cell truly behaves as a second-order dynamical system. The recent extension of the Dynamic Route Map analysis tool to systems with two degrees of freedom constitutes a powerful technique to investigate the nonlinear dynamics of memristive cellular networks in these scenarios. This paper exploits this system-theoretic technique, called Second-Order Dynamic Route Map, to introduce a novel systematic procedure to design memristive arrays, in which a given memcomputing task is executed by ensuring that, depending upon the network inputs and initial conditions, the analogue dynamic routes of the states of the processing elements, namely capacitor voltages and memristor states, asymptotically converge toward pre-defined stable equilibria.

A Strong Subthreshold Current Array PUF Resilient to Machine Learning Attacks

Abstract: This paper presents a strong silicon physical unclonable function (PUF) resistant to machine learning (ML) attacks. The PUF, termed the subthreshold current array PUF (SCA-PUF), consists of a pair of two-dimensional transistor arrays and a low-offset comparator. The proposed 65-bit SCA-PUF is fabricated in a 130nm process and allows 265 challenge-response pairs (CRPs). It consumes 68nW and 11pJ/bit while exhibiting high uniqueness, uniformity, and randomness. It achieves bit error rate (BER) of 5.8% for the temperature range of −20 to 80°C and supply voltage variation of ±10%. The calibration-based CRP selection method improves BER to 0.4% with a 42% loss of CRPs. When subjected to ML attacks, the prediction error stays over 40% on 104 training points, which shows negligible loss in PUF unpredictability and $\sim 100\times $ higher resilience than the 65-bit arbiter PUF, 3-XOR PUF, and 3-XOR lightweight (LW) PUF.

Distributed Consensus of Layered Multi-Agent Systems Subject to Attacks on Edges

Abstract: This paper addresses the consensus problem for two-layered MASs (multi-agent systems) subject to attacks on communication edges. Unlike most existing two-layered MAS models, the considered MASs are allowed to have heterogeneous inner communication topologies between the different layers. By using the linear transformation technique, some sufficient criteria are first given to achieve consensus among the leaders within the leader layer where the condition that the interaction topology has directed spanning trees with a fixed root required in most existing works has been removed. Furthermore, based on the relative outputs, observer-based controllers are designed to achieve node-to-node consensus among the two layers. By developing a new kind of multiple Lyapunov function (MLF) based on a bisection search method, some criteria are established under which the node-to-node consensus error will converge into a bounded set asymptotically. It is interestingly found that a less conservative average dwell time (ADT) constraint is obtained for achieving node-to-node consensus by utilizing the proposed MLF compared with that yielded by the traditional MLF constructed from nonsingular $M$ matrix theory. Moreover, we show that consensus can be achieved asymptotically in the layered MASs with the same inner topology subject to synchronous attacks under some suitable conditions. Finally, the effectiveness of the criteria is verified by simulation on networking linear oscillators.

Fully Distributed Containment Control for Multiple Euler-Lagrange Systems Over Directed Graphs: An Event-Triggered Approach

Abstract: This paper focuses on the distributed containment control problems for multiple Euler-Lagrange systems with stationary/dynamic leaders over directed communication networks. When the leaders are stationary, a distributed event-triggered adaptive control law is presented, and three other update algorithms of the time-varying control gain are further designed for comparison. Then, a distributed event-triggered neural-network-based control protocol is developed when the dynamic leaders are considered. The aforementioned two control strategies can be implemented in fully distributed chattering-free manners since no global information and discontinuous items are employed. In addition, the requirement for relative velocity measurements are relaxed in controller design. The update frequency and energy consumption of the controlled systems are effectively reduced by applying the event-triggered mechanism. It is rigorously verified that the proposed event-triggered control protocols will not be updated infinitely in finite time, which indicates that the undesired Zeno behavior can be ruled out. Finally, the effectiveness of the theoretical results is illustrated by some simulation examples.

H∞ Control for Switched Systems Based on Dynamic Event-Triggered Strategy and Quantization Under State-Dependent Switching

Abstract: This paper is concerned with the $H_\infty $ control problem for switched systems under the event-triggered sampling, the quantization control and the state-dependent switching. The dynamic event-triggered strategy and the quantization control are utilized to adjust the signal transmission and relieve the transmission load. Different from the existing dynamic event-triggered strategies, the triggering condition only needs to be monitored at discrete time. Moreover, the state-dependent switching law is designed by using only the discrete state information. Under the event-triggered sampling, the quantization control and the state-dependent switching, sufficient conditions are proposed to guarantee the $H_\infty $ performance. A switched RLC system is utilized to verify the results in the simulation.

Res-DNN: A Residue Number System-Based DNN Accelerator Unit

Abstract: In this article, a technique, based on using Residue Number System (RNS) is suggested to improve the energy efficiency of Deep Neural Networks (DNNs). In the DNN architecture, which is fully RNS-based, only weights and the primary inputs in the main memory are in the binary number system (BNS). The architecture, which is called Res-DNN, offers a high energy saving while requiring higher bit count for data to handle the overflow compared to that of a BNS one. Scaling techniques in the processing elements are employed in the RNS-based computations to make the computation bit widths the same as the BNS bit width. In this architecture, the MAX pooling and ReLU activation function are implemented in the RNS format. To lower the memory usage and required memory bandwidth, we suggest a Huffman-based coding. Additionally, for accessing the weights stored in the main memory, to obtain further energy reduction, we propose a structural modification to the memory hierarchy where a lower level register file is added to the data path of these accesses. The effectiveness of the proposed architecture is evaluated under seven state-of-the-art DNNs with the datasets of ImageNet and CIFAR-10. The obtained results show that Res-DNN leads to $2.5\times $ lower energy for computations and an average of 30% overall energy reduction compared to those of the binary counterpart.

A Memristive Multiplier Using Semi-Serial IMPLY-Based Adder

Abstract: Memristors are among emerging technologies with many promising features, which makes them suitable not only for storage purposes but also for computations. In this work, focusing on in-memory computations, we first present our semi-serial IMPLY-based adder and perform an extensive analysis of its merits. In addition to providing a favorable balance between the number of steps and number of memristors, a key property of the presented adder is its compactness as compared to the state-ofthe-art adders. Next, using our semi-serial adder, we propose an IMPLY-based multiplier. We show that the proposed multiplier is more than 5× better than other works based on the figure of merit which gives equal weight to the number of steps (i.e., speed) and required die area. Additionally, we provide a deeper insight into IMPLY-based arithmetic units, their properties, design characteristics, and advantages or disadvantages compared to one another by proposing new figures of merit and performing comprehensive comparative analyses. This facilitates the process of design, or selection, of suitable units for the design engineers and researchers in the field.

A Robust 8-Bit Non-Volatile Computing-in-Memory Core for Low-Power Parallel MAC Operations

Abstract: The Artificial Intelligence (AI) in edge computing is requesting new processing units with a much higher computing-power ratio. The emerging resistive Non-Volatile Memory (NVM) with the in-memory computing capability may greatly advance the AI hardware technologies. In this paper, we propose the use of binary resistive memory to form an 8-bit fixed-point data/weight for AI computing. A robust Computing-In-Memory (CIM) core with digital input and analog output Multiplication-and-Accumulation (MAC) circuit is proposed. The corresponding integration scheme and Successive Approximation Register Analog-to-Digital Converter (SAR ADC) based data conversion scheme are also presented. The simulation results show that the proposed CIM core achieves 7.26 bit of Effective Number of Bits (ENOB) with 0.78mW (256*1) power consumption and 1.85M/s computing speed. Compared with previously reported CIM implementations and Deep Learning Accelerators (DLAs) (without CIM ability), our design achieves 2.23– $7.26\times $ better energy efficiency in 8-bit input 8-bit weight pattern, and achieves relatively high accuracy with LeNet and AlexNet.

Processing Near Sensor Architecture in Mixed-Signal Domain With CMOS Image Sensor of Convolutional-Kernel-Readout Method

Abstract: In the era of Artificial Intelligence (AI), bio-inspired perceptual computing system design brings favorable opportunities, while still facing considerable challenges in the meantime. Especially for tasks of image recognition in power-limited vision-based Internet of Things (IoT) devices, energy constraints due to the end of Dennard scaling limit the performance of Neural Network (NN) algorithms on popular digital platforms, which would not reach the energy efficiency requirement for embedded AI applications. In this paper, a processing near sensor architecture in mixed-signal domain with CMOS Image Sensor (CIS) of convolutional-kernel-readout method is proposed. Visual data is collected from a smart CIS, which can realize maximum $5 \times 5$ kernel-readout with minimum one slide step for convolutional operations. The outputs of CIS are directly processed by analog processing units locating near CIS without the constraint of digital clock and bottleneck of Analog-to-Digital Converter (ADC). By analyzing the effects of analog noise on classification accuracy, we further evaluate the fault-tolerance of the system to circuit noise and the device imperfection, such as mismatch and process variation. A mixed-signal visual perception chip is fabricated with a $32\times32$ image sensor and a Binarized Neural Network (BNN) processing array integrated with SMIC 180nm standard CMOS mixed-signal process. Measurement results show up to 545.4 GOPS/W energy efficiency with 1.8mW power consumption taking the advantages of ADC-free processing architecture. This work provides a promising alternative for low-power vision-based IoT intelligent applications.