Supply chain management issues have become increasingly important to the semiconductor industry over the last two decades due to the global distribution of facilities and increasing numbers of firm...

A survey of semiconductor supply chain models part I: semiconductor supply chains, strategic network design, and supply chain simulation

The present invention provides a system and method for assessing the status of work waiting for service in a work queue or a work pool. Work items are placed in the work queue or work pool and have a service time goal. The work items in the work queue or work pool are scanned and a required queue position for each work item is calculated according to the amount of time remaining prior to the expiration of the service time goal and weighted advance time for servicing of work items in the work queue or pool. An array of counters has elements which correspond to required queue positions. Upon the calculation of the required queue position for a work item, the counter corresponding to the required queue position is incremented. When all of the work items are scanned, the array of counters is analyzed to predict a future state of the work queue or work pool.

Method and apparatus for assessing the status of work waiting for service

An intelligent system for wafer bin map defect diagnosis: An empirical study for semiconductor manufacturing

With the shrinking feature size of integrated circuits driven by continuous technology migrations for wafer fabrication, the control of tightening critical dimensions is critical for yield enhancem...

Analysing semiconductor manufacturing big data for root cause detection of excursion for yield enhancement

Root cause detecting and rapid yield ramping for advanced technology nodes are crucial to maintain competitive advantages for semiconductor manufacturing. Since the data structure is increasingly complicated in a fully automated wafer fabrication facility, it is difficult to diagnose the whole production system for fault detection. A number of approaches have been proposed for fault diagnosis and root cause detection. However, many constraints in real settings restrict the usage of conventional approaches, due to the big data with complicated data structure. In particular, a batch may not be considered as a run in the present sub-batch processing system for wafer fabrication, in which the processing paths of the wafers in a batch could be different. Motivated by realistic needs, this paper aims to develop a root cause detection framework for the sub-batch processing system. Briefly, the proposed framework consists of three phases: data preparation, data dimension reduction, and the sub-batch processing model construction and evaluation. The proposed approach has been validated by a sequence of simulations and an empirical study conducted in a leading semiconductor manufacturing company in Taiwan. The results have shown practical viability of the proposed approach. Indeed, the developed approach is incorporated in the engineering data analysis system in this case company.

A Framework for Root Cause Detection of Sub-Batch Processing System for Semiconductor Manufacturing Big Data Analytics

This paper presents a brief overview of semiconductor manufacturing followed by the results of a panel session held at the Fourth International Conference on Modeling and Analysis of Semiconductor Manufacturing (MASM) in Miami, December 10, 2008 on the role of modelling and analysis in semiconductor manufacturing in a shrinking world. Three participants are from Asia, two from Europe, and two from the USA in addition to the two panel organisers (Fowler and Monch). At least one panellist from each continent is from industry and one from academia. The statements of the panellists from industry relate to modelling and analysis problems found in their own companies. Those of the academic panellists describe the role that modelling and analysis has played and is expected to play in their semiconductor manufacturing research. Their views on the challenges and successes of modelling and analysis in a globalised world are also included. Finally, we identify some future research challenges for semiconductor manufa...

Modelling and analysis of semiconductor manufacturing in a shrinking world: challenges and successes

A panel session on the role of modeling and analysis in semiconductor manufacturing in a shrinking world is presented. Therefore, two participants are from Asia, two from Europe, and two from US and there are two panel organizers/ moderators (Fowler and Monch). One panelist from each continent is from industry and one from academia. Only initial position statements are included in the proceedings. However, these initial statements form the basis for the panel discussion. The statements of the panelists from industry relate to modeling and analysis problems found in their own companies. The position statements of the panelists from academia describe the role that modeling and analysis is expected to play in their current and ongoing research in semiconductor manufacturing. Furthermore, their views on the challenges and successes of modeling and analysis in a globalized world are also included.

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Modeling and analysis of semiconductor manufacturing in a shrinking world: challenges and successes

A significant challenge in implementing the Theory of Constraints in the semiconductor industry is the complex and reentrant nature of the manufacturing process Managing a constraint or bottleneck in such processes is resultingly complex and is an ongoing topic of research The paper describes a straightforward method to avoid starvation of possibly recurring bottleneck equipment This method is not proximity sensitive, meaning that it does not act on material only if it is within a specified proximity of the constraint This method is capable of reacting to changes in product mix and can act to correct line imbalances since it is based on real time data from the floor control system The assertion is also made that for the case where a bottleneck has several occurrences in the product flow, all occurrences of the bottleneck must avoid starvation, not just the overall equipment queue This affects the ability of the primary constraint to feed itself

/pdf/implementing-the-theory-of-constraints-philosophy-in-highly-1womw1126x.pdf

Implementing the theory of constraints philosophy in highly reentrant systems

A processing system includes a scheduling system to scheduling processing of lots which are distributed among various processing system stations. Process scheduling is determined in accordance with lot specific composite ratios which are a function of process scheduling factors. Such process scheduling factors include, for example, a processing system efficiency, customer factors, and market factors. Processing system efficiency is influenced by a hunger ratio which is a ratio of the time when a particular lot is needed by a next constraint resource in the lot's process flow and the planned cycle time of a select lot to such next constraint resource. Customer factors include a critical ratio of the lateness of a lot relative to the lot's due date, and market factors reflect the relevant market priority of the lot. The process scheduling factors may be weighted to control their influence on the composite ratio.

Shekar Krishnaswamy

Papers

Modelling and analysis of semiconductor manufacturing in a shrinking world: challenges and successes

Modeling and analysis of semiconductor manufacturing in a shrinking world: challenges and successes

Implementing the theory of constraints philosophy in highly reentrant systems

Processing system having a scheduling system based on a composite ratio of process scheduling factors