Showing papers by "Shey-Shi Lu published in 2010"

Analysis and Design of a CMOS UWB LNA With Dual- $RLC$ -Branch Wideband Input Matching Network

Abstract: A wideband low-noise amplifier (LNA) based on the current-reused cascade configuration is proposed. The wideband input-impedance matching was achieved by taking advantage of the resistive shunt-shunt feedback in conjunction with a parallel LC load to make the input network equivalent to two parallel RLC-branches, i.e., a second-order wideband bandpass filter. Besides, both the inductive series- and shunt-peaking techniques are used for bandwidth extension. Theoretical analysis shows that both the frequency response of input matching and noise figure (NF) can be described by second-order functions with quality factors as parameters. The CMOS ultra-wideband LNA dissipates 10.34-mW power and achieves S 11 below -8.6 dB, S 22 below -10 dB, S 12 below -26 dB, flat S 21 of 12.26 ± 0.63 dB, and flat NF of 4.24 ± 0.5 dB over the 3.1-10.6-GHz band of interest. Besides, good phase linearity property (group-delay variation is only ±22 ps across the whole band) is also achieved. The analytical, simulated, and measured results agree well with one another.

Analysis and Design of a 1.6–28-GHz Compact Wideband LNA in 90-nm CMOS Using a $ \pi $ -Match Input Network

Abstract: This paper presents a wideband low-noise amplifier (LNA) based on the cascode configuration with resistive feedback. Wideband input-impedance matching was achieved using a shunt-shunt feedback resistor in conjunction with a preceding π -match network, while the wideband gain response was obtained using a post-cascode inductor (LP), which was inserted between the output of the cascoding transistor and the input of the shunt-shunt resistive feedback network to enhance the gain and suppress noise. Theoretical analysis shows that the frequency response of the power gain, as well as the noise figure (NF), can be described by second-order functions with quality factors or damping ratios as parameters. Implemented in 90-nm CMOS technology, the die area of this wideband LNA is only 0.139 mm2 including testing pads. It dissipates 21.6-mW power and achieves S11 below -10 dB, S22 below -10 dB, flat S21 of 9.6 ±1.1 dB, and flat NF of 3.68 ± 0.72 dB over the 1.6-28-GHz band. Besides, excellent input third-order inter-modulation point of +4 dBm is also achieved. The analytical, simulated, and measured results are mutually consistent.

Pain Control on Demand Based on Pulsed Radio-Frequency Stimulation of the Dorsal Root Ganglion Using a Batteryless Implantable CMOS SoC

Abstract: This paper presents the implementation of a batteryless CMOS SoC with low voltage pulsed radio-frequency (PRF) stimulation. This implantable SoC uses 402 MHz command signals following the medical implanted communication system (MICS) standard and a low frequency (1 MHz) for RF power transmission. A body floating type rectifier achieves 84% voltage conversion ratio. A bi-phasic pulse train of 1.4 V and 500 kHz is delivered by a PRF driver circuit. The PRF parameters include pulse duration, pulse frequency and repetition rate, which are controllable via 402 MHz RF receiver. The minimal required 3 V RF Vin and 2.2 V VDDr is achieved at 18 mm gap. The SoC chip is fabricated in a 0.35 μm CMOS process and mounted on a PCB with a flexible spiral antenna. The packaged PRF SoC was implanted into rats for the animal study. Von Frey was applied to test the mechanical allodynia in a blinded manner. This work has successfully demonstrated that implanted CMOS SoC stimulating DRG with 1.4 V, 500 kHz PRF could significantly reduce spinal nerve ligation (SNL) induced mechanical allodynia for 3-7 days.

Implantable pulsed-radiofrequency micro-stimulation system

Abstract: The present invention relates to a method for treating a nervous symptom or condition in a subject with a pulsed-radiofrequency stimulation system with a low voltage to overcome the disadvantages of the known related stimulation systems

A Programmable Edge-Combining DLL With a Current-Splitting Charge Pump for Spur Suppression

Abstract: A programmable edge-combining delay-locked loop (DLL) with fast switching transient and reduced output spur is presented in this work. With 12 delay cells adopted in the DLL, the programmable frequency-multiplied output can be quickly switched between ×6, ×3, and ×2 without affecting the lock state of the DLL. Output spur is suppressed by reducing the DLL phase offset in the lock state, which is achieved by decreasing the charge-pump (CP) current during the idle interval of the phase detector. The proposed DLL frequency synthesizer, which has been realized in a CMOS 90-nm technology, consumes 20 mW at 1.2 V supply with the frequency-multiplied output covering from 0.45 to 5.4 GHz. For 850-MHz input clock, the phase noise at 1-MHz frequency offset after ×6, ×3, and ×2 is -121.4, -127.4, and -129.7 dBc/Hz, respectively. The corresponding output spurs achieve -26.2, -36.8, and -39.2 dBc for ×6, ×3, and ×2, which are 7.6, 5.9, and 15.4 dB lower than those using a conventional current-steering CP, respectively.

Pain control on demand based on pulsed radio-frequency stimulation of the dorsal root ganglion using a batteryless implantable CMOS SoC

Abstract: Although pain is interpreted as the fifth vital sign by many professions, the presence of different degrees of pain significantly affects quality of life for many patients, especially the elderly [1]. Electrical stimulation to the central or peripheral neural conduction paths has been utilized in clinics to achieve effective pain relief [2]. The conventional scheme for pulsed radio-frequency (PRF) pain therapy uses thermal coagulation to permanently damage nerves by heat. This destructive method can cause severe side-effects such as hyper-sensitivity to pain after nerves regenerate. Thus, repeated surgery is needed. Additionally, the conventional design of an implantable system requires a battery for operation, often accounting for over 2/3 of the entire device volume. Therefore, a non-destructive and batteryless method using PRF for pain control is key for implantable systems. This work uses a batteryless implantable pain-control SoC that is effective in pain reduction, using a low stimulation voltage that avoids causing thermal damage to dorsal root ganglion (DRG) tissue. An animal study of neuropathic pain was previously designed with PRF parameters to control tissue temperature at ≪40°C via an external function generator [3]. This work now presents the implementation of this functionality on a CMOS SoC. Its effectiveness is demonstrated by observing the behavior of rats receiving localized bipolar stimulus to the DRG of the lumbar nerve.

A 2.1 to 6 GHz Tunable-band LNA With Adaptive Frequency Responses by Transistor Size Scaling

Abstract: A 2.1 to 6 GHz tunable-band LNA by using transistor-size scaling technique is realized in 90 nm CMOS technology, which adopts a scalable-size transistor mimicked by the parallel-connected transistors with binary weighted device sizes. In the 16 programmable bands located in the frequencies of interest, the S21 varies in the range from 15.1 to 16.9 dB, and the NF is from 2.16 to 2.81 dB. This tunable -band LNA occupies only 0.23 mm2, which is readily compact compared with the prior arts of passive components switchable LNAs.

Computer system and method for providing assistance in the preparation of a patent application

Abstract: A computer system capable of providing assistance in the preparation of a patent application is provided. The computer system includes a database group. The database group includes a case database for storing a case file. The case database includes a drawing data storage for storing at least one drawing of an embodiment of an invention that is the subject of a patent application and that corresponds to the case file. The at least one drawing includes at least one component reference numeral. The case database further includes a component description data storage for storing component-descriptive text of at least one component of the embodiment that corresponds to the case file, the at least one component corresponding to the at least one component reference numeral included in the at least one drawing stored in the drawing data storage.

A 4.9-dB NF 53.5-to 62-GHz MICROMACHINED CMOS WIDEBAND LNA WITH SMALL GROUP-DELAY-VARIATION

Abstract: A 53.5- to 62-GHz wideband low-noise amplifier (LNA) with excellent phase linearity property using standard 0.13 μm CMOS technology is reported.To achieve sufficient gain, the LNA is composed of six cascade common-source stages. Current-sharing technique is adopted to reduce power dissipation. The LNA (STD LNA) consumed 29.1 mW and achieved input return loss (S11) of −10.3 to −19.5 dB, output return loss (S22) of −13.8 to −27.8 dB, forward gain (S21) of 8.1 to 11.1 dB, and reverse isolation (S12) of −49.9 to −60.2 dB over the 53.5- to 62-GHz-band. The minimum NF (NFmin) is 5.4 dB at 62 GHz. To reduce the substrate loss, the CMOS process compatible backside inductively-coupled-plasma (ICP) deep trench technology is used to selectively remove the silicon underneath the LNA. After the ICP etching, the LNA (ICP LNA) achieved maximum S21 (S21-max) of 13.2 dB (at 58 GHz), 2.1 dB higher than that (11.1 dB) of the STD LNA (at 58.5 GHz). In addition, the ICP LNA achieved NFmin of 4.9 dB (at 61 GHz), 0.5 dB lower than that (5.4 dB) of the STD LNA (at 62 GHz). These results demonstrate the proposed LNA architecture in conjunction with the backside ICP deep-trench technology is very promising for high-performance 60-GHz-band RFIC applications. © 2010 Wiley Periodicals, Inc. Microwave Opt Technol Lett 52:2427–2432, 2010; View this article online at wileyonlinelibrary.com. DOI 10.1002/mop.25500

Analysis and design of on-sensor ECG processors for realtime detection of VF, VT, and PVC

Abstract: Cardiovascular disease remains the main cause of death, and great efforts are spent on the design of ECG body sensors these years. Essential components such as analog frontend and wireless transceivers have been integrated on a compact IC with micro-Watt power consumption. To provide timely warning against the fatal vascular signs, based on the Chaotic Phase Space Differential (CPSD) algorithm, on-sensor processors are implemented to detect the abnormal ECG for VF, VT and PVC. The on-sensor processing reduces 98.0% power of wireless data transmission for raw ECG signals. The application specific processor is designed to accelerate CPSD algorithm with 1.7μW power while the OpenRISC is integrated to provide the system flexibility. The architecture is realized on the FPGA platform to physically demonstrate the detection of the abnormal ECG signals in a real time.

A 4.9-dB NF 53.5–62-GHz micro-machined CMOS wideband LNA with small group-delay-variation

Abstract: A 53.5–62-GHz wideband CMOS low-noise amplifier (LNA) with excellent phase linearity property is reported. Current-sharing technique is adopted to reduce power dissipation. The LNA (STD LNA) consumed 29.1 mW and achieved input return loss (S11) of −10.3∼ −19.5 dB, output return loss (S 22 ) of −13.8∼ −27.8 dB, forward gain (S 21 ) of 8.1∼ 11.1 dB, and reverse isolation (S 12 ) of −49.9∼ −60.2 dB over the 53.5–62-GHz-band. The minimum NF (NF min ) is 5.4 dB at 62 GHz. To reduce the substrate loss, the CMOS process compatible backside inductively-coupled-plasma (ICP) deep trench technology is used to remove the silicon underneath the LNA. After the ICP etching, the LNA (ICP LNA) achieved maximum S 21 (S 21-max ) of 13.2 dB, 2.1 dB higher than that (11.1 dB) of the STD LNA. In addition, the ICP LNA achieved NF min of 4.9 dB, 0.5 dB lower than that (5.4 dB) of the STD LNA. These results demonstrate the proposed LNA architecture in conjunction with the backside ICP technology is very promising for 60-GHz-band RFIC applications.

A Single-VCO Fractional- $N$ Frequency Synthesizer for Digital TV Tuners

Abstract: A single-voltage-controlled-oscillator (VCO) fractional-N frequency synthesizer is designed for Advanced Television Systems Committee, Digital Video Broadcasting-Terrestrial, and Integrated Services Digital Broadcasting-Terrestrial digital television tuners. This frequency synthesizer can cover all the frequency bands for all three standards with only one VCO, and thus, the chip area as well as the power consumption can be greatly reduced. Different channel spacing requirements can be fulfilled by fractional synthesis. A dynamic frequency calibration loop is also used to automatically choose the coarse setting of the VCO. The synthesizer was fabricated in a standard 0.13-μm complementary metal-oxide-semiconductor process and draws 14 mA from a 1.2-V supply. The measured phase noise is lower than -80 dBc/Hz from 1 to 100 kHz offset and -100 dBc/Hz at 1 MHz offset. The active area of the frequency synthesizer is smaller than 0.54 mm2.

Phase-locked loop circuit and an associated method

Abstract: The present invention relates to a PLL circuit and an associated method that allows the PLL circuit to operate at a higher operating frequency with a wider bandwidth and a better out-band noise suppression. The PLL circuit comprises a delay locked loop (DLL), a phase-frequency detector (PFD), a loop filter, a voltage controlled oscillator (VCO) and a frequency divider.

Dual mode rf transceiver and receiving method of the same

Abstract: A dual mode RF transceiver is provided. The dual mode RF transceiver comprises an antenna, a differential low noise amplifier (LNA), a local oscillator and a dual mode differential mixer. The differential LNA receives an RF signal from the antenna to generate a differential amplified RF signal. The dual mode differential mixer comprises a switch module, a plurality of fundamental mixers and a plurality of sub-harmonic mixers. The fundamental mixers are activated in a first receiving mode to generate a first differential baseband signal according to a multiphase local oscillating (LO) signal from the local oscillator and the differential amplified RF signal. The sub-harmonic mixers are activated in a second receiving mode to generate a second differential baseband signal according to the multiphase LO signal from the local oscillator and the differential amplified RF signal. An RF signal receiving method is disclosed herein as well.

Electromagnetic wave absorption component and device

Abstract: The invention provides electromagnetic wave absorption components and device The electromagnetic wave absorption component includes an electromagnetic shield constituted by at least one material selected from the group consisting of a carbon nanocoil and a carbon fiber, and a solidified layer formed of a mixture of a solidifiable material and the electromagnetic shield after solidification Another embodiment of the electromagnetic wave absorption component includes an electromagnetic shield constituted by at least one material selected from the group consisting of a carbon nanocoil and a carbon fiber, and a solidified layer, formed by solidifying a solidifiable material, applicable to encapsulating the electromagnetic shield Further, the electromagnetic wave absorption device is formed by stacking at least two of the above-mentioned electromagnetic wave absorption components

Visual distance warning system

Abstract: The present invention is a visual distance warning system, especially to prevent a user's eyes is too close to a given object The visual distance warning system comprises at least one wireless module, which the wireless module disposes on a user's eyes and/or a visual object, by sorting transmitting/receiving signal's strength or timing to notify the distance between eye and visual object When the signal's strength is greater than certain amount of value or the time between transmitting/receiving times is too short, the visual distance warming system will notice the user

9.8 mW CMOS frequency synthesiser for mode-I UWB transceivers

Abstract: A low-power frequency synthesiser for mode-I UWB transceivers was fabricated in a 90 nm CMOS process. With proper frequency planning and single-sideband mixers, only one phase-locked loop is employed in the synthesiser. To reduce power consumption, low voltage operation circuit structures are used, and hence except for the VCO and dividers, the remaining building blocks can operate with a 0.5 V supply voltage, resulting in power consumption of only 9.8 mW.

6.8–10 GHz frequency synthesizer for software-defined-radio

Abstract: A 6.8–10 GHz fractional-N frequency synthesizer for the software-defined-radio is presented in 90-nm CMOS technology. Differentially tuned varactors are employed to achieve a VCO with a wide tuning range and low phase noise. The charge pump current is varied to optimize the loop bandwidth over the entire VCO tuning range from 6.8 GHz to 10 GHz. The power dissipation of the synthesizer chip is 59 mW. The synthesizer achieves the close-in phase noise of −91 dBc/Hz and the reference spur of −68 dBc at the integer-N mode. The synthesizer can settle to the desired frequency within 10∼11 us in each application band while offering a frequency resolution of 3 Hz.

Drug delivery chip and fabricating method thereof

Abstract: A drug-delivery chip and a method of fabricating the same are provided. The drug-delivery chip has a main body having at least one drug receiving space individually formed with an opening for storing drugs therein; a thin film for sealing up the at least one drug receiving space; a first conductive wire connecting to one end of the thin film; a second conductive wire connecting to another end of the thin film; a signal-receiving module for receiving actuated signals; and a control module for applying voltages to first and second wire conductive s according to the actuated signal, thereby generating heat to break off the thin film for the release of a drug or drugs received in the at least one drug receiving space.

A 0.4 – 6 GHz variable-gain driver amplifier for software-defined radio

Abstract: A wideband variable gain driver amplifier with shunt resistive-feedback and cascade topology is proposed for software-defined radio (SDR) application. The proposed wideband driver amplifier is implemented in 90 nm CMOS technology. Measurement results show that the power gain is greater than 10 dB and output matching (S22) is better than −10 dB from 0.4 to 6 GHz. The tunable gain ranges from −3 to 18 dB. The OIP3 and power consumption are 4dBm and 10mW, respectively.

A 50-mW, 386 GHz/mm 2 wideband amplifier in 0.13-µm CMOS technology

Abstract: A wideband amplifier with low power consumption (50 mW) and small chip size (044 mm2) is demonstrated in a 013 µm CMOS technology A power gain of 95 dB is measured with a 3 dB bandwidth covering from 01 GHz to 57 GHz as well as a gain-bandwidth-product (GBW) of 170 GHz The proposed wideband amplifier has distinguished itself with the state-of-the-art performance of GBW/Pdiss (34 GHz/mW) and GBW/chiparea (386 GHz/mm2) [1–4], [6–7] which reveals its ability in accomplishing a wideband amplification with reasonable power and area consumptions

Carbon materials for EM wave absorption in V band applications

Abstract: Carbon materials such as carbon fibers, carbon microcoils, graphite, carbon black and ink are used for EM wave absorption in V band for the first time. It is evidenced that that chrial (asymmetric) geometry and smaller grain sizes improve the absorption ratio. It is also found that by painting the carbon ink on papers, EM wave absorption can be also realized.