J
Jung-Suk Goo
Researcher at GlobalFoundries
Publications - 82
Citations - 1687
Jung-Suk Goo is an academic researcher from GlobalFoundries. The author has contributed to research in topics: Strained silicon & MOSFET. The author has an hindex of 23, co-authored 82 publications receiving 1654 citations. Previous affiliations of Jung-Suk Goo include Stanford University & Advanced Micro Devices.
Papers
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Journal ArticleDOI
A noise optimization technique for integrated low-noise amplifiers
TL;DR: In this article, the authors proposed a noise optimization method for low-noise amplifier (LNA) designs based on measured fournoise parameters and two-port noise theory, which can achieve near NF/sub min/ by choosing an appropriate device geometry along with an optimal bias condition.
Patent
FinFET device incorporating strained silicon in the channel region
TL;DR: In this article, an epitaxial layer of silicon is formed on the silicon germanium FinFET body, and a strain is induced in the silicon crystalline lattice to enhance carrier mobility.
Proceedings ArticleDOI
Transistors with dual work function metal gates by single full silicidation (FUSI) of polysilicon gates
TL;DR: The metal gate electrodes with two different work functions were obtained by single-step full silicidation of poly gates as discussed by the authors, and the reduction of polysilicon depletion was /spl sim/0.25 nm.
Journal ArticleDOI
An accurate and efficient high frequency noise simulation technique for deep submicron MOSFETs
Jung-Suk Goo,Chang-Hoon Choi,Francois Danneville,Eiji Morifuji,Hisayo Momose,Zhiping Yu,Hiroshi Iwai,Thomas H. Lee,Robert W. Dutton +8 more
TL;DR: In this article, an accurate and computationally efficient simulation technique for high frequency noise performance of MOSFETs is demonstrated based on an active transmission line concept and two-dimensional (2D) device simulations.
Journal ArticleDOI
MOS C-V characterization of ultrathin gate oxide thickness (1.3-1.8 nm)
Chang-Hoon Choi,Jung-Suk Goo,Tae-Young Oh,Zhiping Yu,Robert W. Dutton,Amr M. Bayoumi,Min Cao,P.V. Voorde,D. Vook,Carlos H. Diaz +9 more
TL;DR: In this paper, an equivalent circuit approach to MOS capacitancevoltage (C-V) modeling of ultrathin gate oxides (1.3-1.8 nm) is proposed.