Modern computers are based on the von Neumann architecture in which computation and storage are physically separated: data are fetched from the memory unit, shuttled to the processing unit (where computation takes place) and then shuttled back to the memory unit to be stored. The rate at which data can be transferred between the processing unit and the memory unit represents a fundamental limitation of modern computers, known as the memory wall. In-memory computing is an approach that attempts to address this issue by designing systems that compute within the memory, thus eliminating the energy-intensive and time-consuming data movement that plagues current designs. Here we review the development of in-memory computing using resistive switching devices, where the two-terminal structure of the devices, their resistive switching properties, and direct data processing in the memory can enable area- and energy-efficient computation. We examine the different digital, analogue, and stochastic computing schemes that have been proposed, and explore the microscopic physical mechanisms involved. Finally, we discuss the challenges in-memory computing faces, including the required scaling characteristics, in delivering next-generation computing. This Review Article examines the development of in-memory computing using resistive switching devices.

/pdf/in-memory-computing-with-resistive-switching-devices-1mv368csjy.pdf

In-memory computing with resistive switching devices

von Neumann architecture based computers isolate computation and storage (i.e. data is shuttled between computation blocks (processor) and memory blocks). The to-and-fro movement of data leads to a fundamental limitation of modern computers, known as the Memory wall. Logic in-Memory (LIM)/In-Memory Computing (IMC) approaches aim to address this bottleneck by directly computing inside memory units thereby eliminating energy-intensive and time-consuming data movement. Several recent works in literature, propose realization of logic function(s) directly using arrays of emerging resistive memory devices (example- memristors, RRAM/ReRAM, PCM, CBRAM, OxRAM, STT-MRAM etc.), rather than using conventional transistors for computing. The logic/embedded-side of digital systems (like processors, micro-controllers) can greatly benefit from such LIM realizations. However, the pure storage-side of digital systems (example SSDs, enterprise storage etc.) will not benefit much from such LIM approaches as when memory arrays are used for logic they lose their core functionality of storage. Thus, there is the need for an approach complementary to existing LIM techniques, that's more beneficial for the storage-side of digital systems; one that gives compute capability to memory arrays not at the cost of their existing stored states. Fundamentally, this would require memory nanodevice arrays that are capable of storing and computing simultaneously. In this paper, we propose a novel 'Simultaneous Logic in-Memory' (SLIM) methodology which is complementary to existing LIM approaches in literature. Through extensive experiments we demonstrate novel SLIM bitcells (1T-1R/2T-1R) comprising non-filamentary bilayer analog OxRAM devices with NMOS transistors. Proposed bitcells are capable of implementing both Memory and Logic operations simultaneously. Detailed programming scheme, array level implementation, and controller architecture are also proposed. Furthermore, to study the impact of proposed SLIM approach for real-world implementations, we performed analysis for two applications: (i) Sobel Edge Detection, and (ii) Binary Neural Network- Multi layer Perceptron (BNN-MLP). By performing all computations in SLIM bitcell array, huge Energy Delay Product (EDP) savings of ≈75× for 1T-1R (≈40× for 2T-1R) SLIM bitcell were observed for edge-detection application while EDP savings of ≈3.5× for 1T-1R (≈1.6× for 2T-1R) SLIM bitcell were observed for BNN-MLP application respectively, in comparison to conventional computing. EDP savings owing to reduction in data transfer between CPU ↔ memory is observed to be ≈780× (for both SLIM bitcells).

/pdf/slim-simultaneous-logic-in-memory-computing-exploiting-48akr75xhf.pdf

SLIM: Simultaneous Logic-in-Memory Computing Exploiting Bilayer Analog OxRAM Devices.

The rapid increase in information in the big-data era calls for changes to information-processing paradigms, which, in turn, demand new circuit-building blocks to overcome the decreasing cost-effectiveness of transistor scaling and the intrinsic inefficiency of using transistors in non-von Neumann computing architectures. Accordingly, resistive switching materials (RSMs) based on different physical principles have emerged for memories that could enable energy-efficient and area-efficient in-memory computing. In this Review, we survey the four physical mechanisms that lead to such resistive switching: redox reactions, phase transitions, spin-polarized tunnelling and ferroelectric polarization. We discuss how these mechanisms equip RSMs with desirable properties for representation capability, switching speed and energy, reliability and device density. These properties are the key enablers of processing-in-memory platforms, with applications ranging from neuromorphic computing and general-purpose memcomputing to cybersecurity. Finally, we examine the device requirements for such systems based on RSMs and provide suggestions to address challenges in materials engineering, device optimization, system integration and algorithm design. Resistive switching materials enable novel, in-memory information processing, which may resolve the von Neumann bottleneck. This Review focuses on how the switching mechanisms and the resultant electrical properties lead to various computing applications.

Resistive switching materials for information processing

https://re.public.polimi.it/bitstream/11311/1049036/1/mee_2018.pdf

Brain-inspired computing with resistive switching memory (RRAM): Devices, synapses and neural networks

Emerging Artificial Synaptic Devices for Neuromorphic Computing

Resistance switching (RS) devices have potential to offer computing and memory function. A new computer unit is built of RS array, where processing and storing of information occur on same devices. Resistance states stored in devices located in arbitrary positions of RS array can be performed various nonvolatile logic operations. Logic functions can be reconfigured by altering trigger signals.

Reconfigurable Nonvolatile Logic Operations in Resistance Switching Crossbar Array for Large-Scale Circuits.

HfOx-based resistive switching device has been explored as one of the promising candidates for the electronic synapses of neuromorphic computing systems due to its high performance, low cost, and compatibility with CMOS technology. To meet the codesign requirement of HfOx-based electronic synapses with CMOS neurons in the neuromorphic computing systems, a compact model that can capture the synaptic futures of HfOx-based resistive switching device is developed. The developed model can accurately describe the multilevel conductance transition behaviors during RESET process for depression learning as well as the binary stochastic transition behavior during SET process for potentiation learning. After the verification with experimental data, the model is used to simulate a winner-take-all neural network to classify patterns with unsupervised competitive learning algorithm. Simulation results imply that the average recognition accuracy would decrease with the increase of the resistance variation of low resistance state (LRS) due to the “trap” effect. Guided by the simulation, a synapse cell consisted of a HfO X -based device and a fixed resistor series connection is proposed to achieve almost 100% recognition accuracy even if the resistance variation of LRS is 50%.

Compact Model of HfO X -Based Electronic Synaptic Devices for Neuromorphic Computing

A high-K/metal gate (HKMG)-stack (TiN/Al-doped-HfO x /SiO2/Si)-based bipolar resistive random access memory (RRAM) cell is proposed and fabricated by 28/20-nm HKMG CMOS compatible technology. Robust reliability behaviors (retention at $200~ {^{\circ }}\text {C} > 4 \times 10^{4}$ s and endurance $> 10^{{{5^{\vphantom {\frac {}{,}}}}}}$ cycles) and ultralow switching current ( $ for RESET and $ for SET) are both demonstrated. The sub- $\mu \text{A}$ switching current and self-selection nonlinear $I$ – $V$ characteristics are attributed to the SiO2 interfacial layer rather than the decrease of conductive filament size and oxygen vacancy ( $V_{O}$ ) density, which can be verified by HRTEM and measured conduction behavior. Therefore, robust reliability property is also achieved. The demonstrated excellent memory characteristics of HKMG stacked RRAM cell enable constituting 1-Mb workable crosspoint array even though the feature size scales down to 10 nm according to the HSPICE simulation.

Self-Selection RRAM Cell With Sub- $\mu \text{A}$ Switching Current and Robust Reliability Fabricated by High- $K$ /Metal Gate CMOS Compatible Technology

A high-K/metal gate (HKMG) stack (TiN/Al-doped-HfO X /SiO 2 /Si) based bipolar RRAM cell is proposed and fabricated by 28/20nm HKMG CMOS compatible technology. Robust reliability behaviors (retention @200 °C >4×104 s and endurance > 105) and sub-μA switching current are both demonstrated. The sub-μA switching current and self-selection nonlinear I–V characteristics are attributed to the SiO 2 interfacial layer rather than the decrease of conductive filament (CF) size and oxygen vacancy (V O ) density, which can be verified by HRTEM and measured conduction behavior. Therefore, robust reliability property is also achieved. The demonstrated excellent memory characteristics of HKMG stacked RRAM cell can constitute workable 1 Mb crosspoint array when feature size scales down to 10 nm according to the HSPICE simulation.

Sijie Chen

Papers

Reconfigurable Nonvolatile Logic Operations in Resistance Switching Crossbar Array for Large-Scale Circuits.

Compact Model of HfO X -Based Electronic Synaptic Devices for Neuromorphic Computing

Self-Selection RRAM Cell With Sub- $\mu \text{A}$ Switching Current and Robust Reliability Fabricated by High- $K$ /Metal Gate CMOS Compatible Technology

Self-selection RRAM cell with Sub-μA switching current and robust reliability fabricated by high-K/metal gate CMOS compatible technology