The appearance of radix-22 was a milestone in the design of pipelined FFT hardware architectures. Later, radix-22 was extended to radix-2k . However, radix-2k was only proposed for single-path delay feedback (SDF) architectures, but not for feedforward ones, also called multi-path delay commutator (MDC). This paper presents the radix-2k feedforward (MDC) FFT architectures. In feedforward architectures radix-2k can be used for any number of parallel samples which is a power of two. Furthermore, both decimation in frequency (DIF) and decimation in time (DIT) decompositions can be used. In addition to this, the designs can achieve very high throughputs, which makes them suitable for the most demanding applications. Indeed, the proposed radix-2k feedforward architectures require fewer hardware resources than parallel feedback ones, also called multi-path delay feedback (MDF), when several samples in parallel must be processed. As a result, the proposed radix-2k feedforward architectures not only offer an attractive solution for current applications, but also open up a new research line on feedforward structures.

/pdf/pipelined-radix-2-k-feedforward-fft-architectures-5dku5xiwia.pdf

Pipelined Radix- $2^{k}$ Feedforward FFT Architectures

This paper presents an multipath delay commutator (MDC)-based architecture and memory scheduling to implement fast Fourier transform (FFT) processors for multiple input multiple output-orthogonal frequency division multiplexing (MIMO-OFDM) systems with variable length. Based on the MDC architecture, we propose to use radix-Ns butterflies at each stage, where Ns is the number of data streams, so that there is only one butterfly needed in each stage. Consequently, a 100% utilization rate in computational elements is achieved. Moreover, thanks to the simple control mechanism of the MDC, we propose simple memory scheduling methods for input data and output bit/set-reversing, which again results in a full utilization rate in memory usage. Since the memory requirements usually dominate the die area of FFT/inverse fast Fourier transform (IFFT) processors, the proposed scheme can effectively reduce the memory size and thus the die area as well. Furthermore, to apply the proposed scheme in practical applications, we let Ns=4 and implement a 4-stream FFT/IFFT processor with variable length including 2048, 1024, 512, and 128 for MIMO-OFDM systems. This processor can be used in IEEE 802.16 WiMAX and 3GPP long term evolution applications. The processor was implemented with an UMC 90-nm CMOS technology with a core area of 3.1 mm2. The power consumption at 40 MHz was 63.72/62.92/57.51/51.69 mW for 2048/1024/512/128-FFT, respectively in the post-layout simulation. Finally, we analyze the complexity and performance of the implemented processor and compare it with other processors. The results show advantages of the proposed scheme in terms of area and power consumption.

https://ir.nctu.edu.tw:443/bitstream/11536/21355/1/000316801700011.pdf

MDC FFT/IFFT Processor With Variable Length for MIMO-OFDM Systems

This paper presents a low-complexity algorithm and architecture to compute power spectral density (PSD) using the Welch method. The Welch algorithm provides a good estimate of the spectral power at the cost of high computational complexity. We propose a new modified approach to reduce the computational complexity of the Welch PSD computation for a 50% overlap. In the proposed approach, an N/2-point FFT is computed, where N is the length of the window and is merged with the FFT of the previous N/2-point to generate an N-point FFT of the overlapped segment. This requires replacing the windowing operation as a convolution in the frequency domain. Fortunately, the frequency-domain filtering requires a symmetric 3-tap or 5-tap FIR filter for raised cosine windows. The proposed method needs to compute ( L+1) N/2-point FFTs instead of L N-point FFTs, where L is the number of overlapping segments. In the proposed novel merged FFT approach, the even samples are computed exactly, while the odd samples require a shift by a half-sample delay and are estimated using a bidirectional fractional-delay filter. The complexity reduction comes at the cost of slight performance loss due to the approximation used for the implementation of the fractional-delay filter. The performance loss is about 8% using fractional-delay filter with 2 multipliers. A novel architecture is presented based on the proposed algorithm. The proposed architecture not only consumes 33% less energy compared to the original method but also reduces the latency by about 44% for 8 overlapping segments. Further a low-complexity architecture is presented to compute a special case of the short-time Fourier transform based on the proposed PSD computation algorithm.

Low-Complexity Welch Power Spectral Density Computation

This paper presents a multimode FFT processor for wireless personal area network (WPAN), wireless local area network (WLAN), and wireless metropolitan area network (WMAN) applications. Using the proposed flexible-radix-configuration multipath-delay-feedback (FRCMDF) architecture, variable-length/multiple-stream FFTs capable of achieving a high throughput can be performed in a hardware-efficient manner. Based on the FRCMDF structure, a dual-optimized multiplication scheme is also proposed to further improve the area and energy efficiency. In addition, the proposed configuration scheme can provide an architectural support for power scalability across FFT modes. A test chip for the proposed FFT processor has been designed and fabricated using a TSMC-0.18 m CMOS process with a core size of 3.2 mm^2 and a signal-to-quantization-noise ratio (SQNR) of over 40 dB. When the FFT mode is configured to operate as a 2.4 GS/s 512-point FFT at 300 MHz, the measured power consumption is 507 mW. Compared with previous multimode FFT designs, our FFT chip is more area- and energy-efficient as it is able to provide relatively higher throughput per unit area or per unit power consumption. Also, the power scalability across FFT modes is relatively exhibited in the proposed FFT processor.

An Area- and Energy-Efficient Multimode FFT Processor for WPAN/WLAN/WMAN Systems

We present an efficient combined single-path delay commutator-feedback (SDC-SDF) radix-2 pipelined fast Fourier transform architecture, which includes $\log _{2}\textit {N}-1$ SDC stages, and 1 SDF stage. The SDC processing engine is proposed to achieve 100% hardware resource utilization by sharing the common arithmetic resource in the time-multiplexed approach, including both adders and multipliers. Thus, the required number of complex multipliers is reduced to $\log _{4}\textit {N}-0.5$ , compared with $\log _{2}\textit {N}-1$ for the other radix-2 SDC/SDF architectures. In addition, the proposed architecture requires roughly minimum number of complex adders $\log _{2}\textit {N}+1$ and complex delay memory $2\textit {N}+1.5\log _{2}\textit {N}-1.5$ .

A Combined SDC-SDF Architecture for Normal I/O Pipelined Radix-2 FFT

This brief presents a fast Fourier transform (FFT) processor that provides high throughput rate (T.R.) by applying the eight-data-path pipelined approach for wireless personal area network applications. The hardware costs, including the power consumption and area, increase due to multiple data paths and increased wordlength along stages. To resolve these issues, a novel simplification method to reduce the hardware cost in multiplication units of the multiple-path FFT approach is proposed. A multidata scaling scheme to reduce wordlengths while preserving the signal-to-quantization-noise ratio is also presented. Using UMC 90-nm 1P9M technology, a 2048-point FFT processor test chip has been designed, and its 128-point FFT kernel has been fabricated for ultrawideband (UWB) applications and also for verification. The 2048-point FFT processor can provide a T.R. of 2.4 GS/s at 300 MHz with a power consumption of 159 mW. Compared with the four-data-path approach, a power consumption saving of about 30% can be achieved under the same T.R. In addition, the 128-point FFT kernel test chip has a measured power consumption of 6.8 mW with a T.R. of 409.6 MS/s at 52 MHz to meet the UWB standard with a saving in power consumption of about 40%.

A 2.4-GS/s FFT Processor for OFDM-Based WPAN Applications

This paper presents an energy-efficient FFT processor providing high throughput rate for wireless personal area network (WPAN). By using a proposed mixed-memory-access-scheduling (MMAS) scheme in the multipath-delay-feedback (MDF) architecture, energy-efficiency is improved for it provides the same high throughput rate with relatively lower power consumption. A test chip of a 2048-point FFT processor has been designed using UMC 90nm process with a core area of 1.18 mm2 excluding the test module. The proposed 2048-point FFT can provide a high throughput rate of 2.4 GS/s at 300 MHz with power consumption of 127 mW by post-layout simulation. Compared to the referred, a saving in power dissipation of 20% or 45% can be achieved at the same throughput rate.

An energy-efficient MMAS FFT processor for high-rate WPAN applications

Many existing studies on accelerating convolutional neural networks (CNNs) use parallel data operation schemes to increase the throughput. This study proposes area-efficient parallel multiplication unit (PMU) designs for a CNN accelerator that uses parallelization on the output channels of a CNN layer, which parallel multiplies a common feature map pixel with multiple CNN kernel weights. First, tailored PMU designs are proposed for CNNs with specific low-precision 3-to-8-bit weights. Second, the proposed 5-to-8-bit PMU designs are extended with two-clock-cycle operations to develop PMUs for weight precision scalable to 10/12/14/16 bits. Compared to 16-path PMUs directly using carry-save-adder array multipliers, our PMU designs can achieve the area reductions of 28.19%−56.09% and 22.10%−30.71% for 3–8 bit and 10-/12-/14-/ 16-bit weights, respectively. Moreover, a resultant 16-path 16-bit weight PMU is verified through the system-on-chip (SoC) field-programmable gate array (FPGA) implementation to demonstrate the CNN inference.

Area-Efficient Parallel Multiplication Units for CNN Accelerators With Output Channel Parallelization

Binary weight convolutional neural networks (BCNNs) that achieve qualified classification accuracy with reduced operation complexity have been progressively used in convolutional neural networks (CNNs). For BCNN accelerators, long-length accumulation units (AUs) can be considered as essential components. This paper proposes an efficient biasing scheme for BCNN AUs based on probabilistic derivation, aiming to reduce the operation-bit-width by truncating several least significant bits (LSBs) of all operands while compensating for the truncation error. With the pre-calculation using pre-known binary weight values, an AU that enables the proposed biasing method can be realized using minimal adder resources. Through the evaluation of accuracy and hardware performances for an $(8\ \times 100)$ -length 16-bit AU, our design can achieve a great reduction in the area-delay and power-delay products than the level of accuracy degra-dation for 3- to 10-bit truncated LSBs, relative to approaches using the post truncation method.

Song-Nien Tang

Papers

A 2.4-GS/s FFT Processor for OFDM-Based WPAN Applications

An Area- and Energy-Efficient Multimode FFT Processor for WPAN/WLAN/WMAN Systems

An energy-efficient MMAS FFT processor for high-rate WPAN applications

Area-Efficient Parallel Multiplication Units for CNN Accelerators With Output Channel Parallelization

Long-Length Accumulation Unit with Efficient Biasing for Binary Weight CNNs