Showing papers by "Souvik Mahapatra published in 2010"

On the Nature of Shunt Leakage in Amorphous Silicon p-i-n Solar Cells

Abstract: In this letter, we investigate the nature of shunt leakage currents in large-area (on the order of square centimeters) thin-film a-Si:H p-i-n solar cells and show that it is characterized by following universal features: (1) voltage symmetry; (2) power-law voltage dependence; and (3) weak temperature dependence. The voltage symmetry offers a robust empirical method to isolate the diode current from measured “shunt-contaminated” forward dark IV. We find that space-charge-limited current provides the best qualitative explanation for the observed features of the shunt current. Finally, we discuss the possible physical origin of localized shunt paths in the light of experimental observations from literature.

Performance and Reliability Study of Single-Layer and Dual-Layer Platinum Nanocrystal Flash Memory Devices Under NAND Operation

Abstract: Memory window (MW) and the retention of single-layer (SL) and dual-layer (DL) platinum (Pt) nanocrystal (NC) devices are extensively studied before and after program/erase (P/E) cycling. DL devices show better charge storage capability and reliability over the SL devices. Up to 50% improvement in the stored charge is estimated in the DL device over SL when P/E is performed at equal field. Excellent high temperature and postcycling retention capabilities of SL and DL devices are shown. The impact of the interlayer film (ILF) thickness on the retention of the DL structure is reported. While SL devices show poor P/E cycling endurance, DL cycling is shown to meet the minimum requirements of the multilevel cell (MLC) operation.

NBTI lifetime prediction in SiON p-MOSFETs by H/H2 Reaction-Diffusion(RD) and dispersive hole trapping model

Abstract: IDLIN shift due to NBTI is measured using UF-OTF IDLIN method in PNO, RTNO and RTNO+PN SiON p-MOSFETs having a wide range of EOT and %N. Time evolution of IDLIN shift at different stress EOX and T is modeled from ultra-short to long stress time using non-dispersive H/H 2 RD model governed N IT and dispersive N h components. N IT and N h model parameters show consistent E OX and T dependent behavior across all devices. Finally, extrapolated tt F values are obtained for different E OX from conventional power-law fit and the proposed model, and are compared across different measurement delay. Inconsistencies associated with conventional power-law fit extrapolation method are highlighted, which justifies the use of proposed model.

Intrinisic reliability of amorphous silicon thin film solar cells

Abstract: In this paper, we have discussed three intrinsic reliability issues of thin-film -Si∶H solar cells; space charge limited shunt conduction through localized metal-semiconductor-metal structures; shadow degradation in series connected cells in a module, and light induced degradation. Despite their distinct external manifestation, these intrinsic reliability issues appear to share common physical phenomena. For example, the light induced and the shadow degradation may be related because they are described by very similar time-exponents (see Fig. 4c and 6a). While the physics of G are different (e.g. photon induced dissociation for LID and (possibly) electron-hole recombination induced dissociation for shadow degradation), it is likely that they both break SiH bonds and are subsequently follow similar diffusive kinetics. Finally, analogies to CMOS reliability; e.g., shunt conduction related to non uniform conduction through oxides, shadow degradation to bulk defect generation and TDDB in gate dielectric, and light induced degradation to NBTI in PMOS transistors; may help illuminate many aspects of the degradation processes.

Study of P/E Cycling Endurance Induced Degradation in SANOS Memories Under NAND (FN/FN) Operation

Abstract: Program/Erase (P/E) cycling endurance in poly-Si/Al2O3/SiN/SiO2/Si (SANOS) memories is systematically studied. Cycling-induced trap generation, memory window (MW) closure, and eventual stack breakdown are shown to be strongly influenced by the material composition of the silicon nitride (SiN) charge trap layer. P/E pulsewidth and amplitude, as well as starting program and erase flatband voltage (VFB) levels (therefore the overall MW), are shown to uniquely impact stack degradation and breakdown. An electron-flux-driven anode hole generation model is proposed, and trap generation in both SiN and tunnel oxide are used to explain stack degradation and breakdown. This paper emphasizes the importance of SiN layer optimization for reliably sustaining large MW during P/E operation of SANOS memories.

Charging and discharging characteristics of metal nanocrystals in degraded dielectric stacks

Abstract: The conduction mechanisms of dielectric breakdown (BD) in MOS capacitor structure with nanocrystals (NCs) embedded in bi-layer gate stacks (SiO 2 /Al 2 O 3 ) are studied systematically. Using a unique stressing methodology of inducing a BD path in one dielectric layer, the charging and discharging phenomenon of the metal NCs and leakage mechanism in the degraded gate stacks are found to be strongly dependent on the lateral charge tunneling/hopping among the NCs. It is found that the localized BD not only affects charge holding capability of the affected NCs, but also provides a leakage path for the charges stored in the surrounding NCs. Thus, the discharging of NCs via the BD path is not a localized phenomenon.

On the universality of negative bias temperature degradation

Abstract: Over last five years, many industrial/academic research groups have characterized the NBTI degradation through power-law exponents, universality of relaxation, frequency and duty cycle dependencies by using a wide variety of characterization techniques. The scatter in the data has inspired a range of modeling efforts regarding NBTI degradation, with important implications for projected lifetime and technology qualification. In this talk, we will show that the scatter in the data hides a simple universality of the degradation characteristics and that universality of data imposes strict consistency requirements for NBTI theories. We conclude by showing that the existing protocol for qualification and circuit design are theoretically sound, and can be used without significant revision/refinement.

A comprehensive analysis on scaling prospects of dual-bit channel engineered SONOS NOR-flash EEPROM cells

Abstract: Scaling prospects of pre-cycled 2-bit channel engineered SONOS flash EEPROM cells are studied on cells co-doped with compensation and halo implant. The compensation implant is shown to work in long channel cells to optimize bit coupling, read disturb, and program speed. However, co-doping with compensation implant fails at short channel length to reduce read disturb thus bit coupling at safe read V D . The junction engineering scheme is shown as the possible alternative for successful scaling of cells to simultaneously reduce read disturb and bit coupling but at the expense of program speed, which seems detrimental for deep scaling of cells.

Applicability of dual layer metal nanocrystal flash memory for NAND 2 or 3-bit/cell operation: Understanding the anomalous breakdown and optimization of P/E conditions

Abstract: Large memory window (6–9V) program/erase (P/E) cycling endurance is studied for evaluating their suitability for MLC operation. Effect of NC area coverage and device size is evaluated using statistical method. Constant voltage stress (CVS) measurements and 2-D simulations are extensively used to evaluate the impact of carrier; type, fluence, and energy on the defect generation process in the gate stack. Degradation during P and E are isolated to allow individual optimization for improving the cycling reliability. P/E cycling endurance ≫104 at 8V MW and ≫2.5×103 at 9V MW are shown for first time in metal NC memory devices using the proposed distributed cycling scheme.