The long-standing popularity of thermoelectric materials has contributed to the creation of various thermoelectric devices and stimulated the development of strategies to improve their thermoelectric performance. In this review, we aim to comprehensively summarize the state-of-the-art strategies for the realization of high-performance thermoelectric materials and devices by establishing the links between synthesis, structural characteristics, properties, underlying chemistry and physics, including structural design (point defects, dislocations, interfaces, inclusions, and pores), multidimensional design (quantum dots/wires, nanoparticles, nanowires, nano- or microbelts, few-layered nanosheets, nano- or microplates, thin films, single crystals, and polycrystalline bulks), and advanced device design (thermoelectric modules, miniature generators and coolers, and flexible thermoelectric generators). The outline of each strategy starts with a concise presentation of their fundamentals and carefully selected examples. In the end, we point out the controversies, challenges, and outlooks toward the future development of thermoelectric materials and devices. Overall, this review will serve to help materials scientists, chemists, and physicists, particularly students and young researchers, in selecting suitable strategies for the improvement of thermoelectrics and potentially other relevant energy conversion technologies.

Advanced Thermoelectric Design: From Materials and Structures to Devices

The limitation of hot spot cooling in microchips represents an important hurdle for the electronics industry to overcome with coolers yet to exceed the efficiencies required. Nanotechnology-enabled heat sinks that can be magnetophoretically formed onto the hot spots within a microfluidic environment are presented. CrO2 nanoparticles, which are dynamically chained and docked onto the hot spots, establish tuneable high-aspect-ratio nanofins for the heat exchange between these hot spots and the liquid coolant. These nanofins can also be grown and released on demand, absorbing and releasing the heat from the hot spots into the microfluidic system. It is shown that both high aspect ratio and flexibility of the fins have a dramatic effect on increasing the heat sinking efficiency. The system has the potential to offer a practical cooling solution for future electronics.

Dynamic nanofin heat sinks

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Nanostructured thermoelectric materials: current research and future challenge

We study the photoresponse of single-layer MoS(2) field-effect transistors by scanning photocurrent microscopy. We find that, unlike in many other semiconductors, the photocurrent generation in single-layer MoS(2) is dominated by the photothermoelectric effect and not by the separation of photoexcited electron-hole pairs across the Schottky barriers at the MoS(2)/electrode interfaces. We observe a large value for the Seebeck coefficient for single-layer MoS(2) that by an external electric field can be tuned between -4 × 10(2) and -1 × 10(5) μV K(-1). This large and tunable Seebeck coefficient of the single-layer MoS(2) paves the way to new applications of this material such as on-chip thermopower generation and waste thermal energy harvesting.

Large and Tunable Photothermoelectric Effect in Single-Layer MoS2

We study the photoresponse of single-layer MoS2 field- effect transistors by scanning photocurrent microscopy. We find that, unlike in many other semiconductors, the photocurrent generation in single-layer MoS2 is dominated by the photothermoelectric effect and not by the separation of photoexcited electron−hole pairs across the Schottky barriers at the MoS2/electrode interfaces. We observe a large value for the Seebeck coefficient for single-layer MoS2 that by an external electric field can be tuned between −4 × 10 2 and −1 × 10 5 μ VK −1 . This large and tunable Seebeck coefficient of the single-layer MoS2 paves the way to new applications of this material such as on- chip thermopower generation and waste thermal energy harvesting.

Large and Tunable Photothermoelectric Effect in Single-Layer MoS 2

There is a significant need for site-specific and on-demand cooling in electronic, optoelectronic and bioanalytical devices, where cooling is currently achieved by the use of bulky and/or over-designed system-level solutions. Thermoelectric devices can address these limitations while also enabling energy-efficient solutions, and significant progress has been made in the development of nanostructured thermoelectric materials with enhanced figures-of-merit. However, fully functional practical thermoelectric coolers have not been made from these nanomaterials due to the enormous difficulties in integrating nanoscale materials into microscale devices and packaged macroscale systems. Here, we show the integration of thermoelectric coolers fabricated from nanostructured Bi2Te3-based thin-film superlattices into state-of-the-art electronic packages. We report cooling of as much as 15 degrees C at the targeted region on a silicon chip with a high ( approximately 1,300 W cm-2) heat flux. This is the first demonstration of viable chip-scale refrigeration technology and has the potential to enable a wide range of currently thermally limited applications.

On-chip cooling by superlattice-based thin-film thermoelectrics

One example electronic assembly includes a substrate that has a plurality of contacts which become bonded to a plurality of contacts on a die. The electronic assembly further includes a male member that extends from at least one of the substrate and the die and a female member that extends from the other of the substrate and the die. The male member is inserted into the female member to align the die relative to the substrate. The male member and the female member may have any configuration as long as one or more portions of the male member extend partially, or wholly, into the female member. An example method includes aligning a die relative to a substrate by inserting a male member that extends from one of the die and the substrate into a female member that extends from the other of the die and the substrate.

Soldering a die to a substrate

A microelectronic package includes first substrate ( 120 ) having first surface area ( 125 ) and second substrate ( 130 ) having second surface area ( 135 ). The first substrate includes first set of interconnects ( 126 ) having first pitch ( 127 ) at first surface ( 121 ) and second set of interconnects ( 128 ) having second pitch ( 129 ) at second surface ( 222 ). The second substrate is coupled to the first substrate using the second set of interconnects and includes third set of interconnects ( 236 ) having third pitch ( 237 ) and internal electrically conductive layers ( 233, 234 ) connected to each other with microvia ( 240 ). The first pitch is smaller than the second pitch, the second pitch is smaller than the third pitch, and the first surface area is smaller than the second surface area.

Microelectronic package and method for a compression-based mid-level interconnect

Solid state refrigeration technologies claim no moving parts and could possibly be one of the promising technologies for electronic cooling in the future. This paper focuses on the use of a thin film thermoelectric cooler (TFTEC) directly above the hotspot to provide localized cooling. We discuss different packaging concepts including placing the TFTEC within the silicon die, between the silicon die and the copper integral heat spreader (IHS), and embedded in the IHS. Estimates of the cooling performance of each concept are provided. In addition, we discuss the modeling approaches including the required TFTEC performance parameters, heat flux through the cold side of the TFTEC device and the temperature difference of the extreme outside surface of the TFTEC device, that impact the targeted hotspot cooling. We also report the requirement curves of those two parameters in order to provide the targeted hotspot temperature reduction. Modeling results show that the performance requirements depend significantly on TFTEC efficiency which would also be discussed in this paper

Feasibility study of using solid state refrigeration technologies for electronic cooling

The shrinking transistor feature sizes have resulted broadly in two different packaging thermal challenges; cooling the total thermal design power of the microprocessor, and thermal suppression of the hot spots which have progressively higher heat fluxes through silicon generations. Solid-state thin film thermoelectric coolers offer a possible solution strategy to the hot spot problems by mitigating the thermal non-uniformity of the silicon. However, considerable challenges are present in incorporating the thermoelectric coolers into a test device and thermal characterization of the prototypes. The present work captures the experimental and thermal modeling methodology that was used to characterize the thermal-electrical behavior of the prototypes. This characterization was followed up with a validation of the prototype over a range of uniform and hot spot heating. A temperature variation of less than 1/spl deg/C in T/sub j/ between the experimental and modeling results were seen. In addition, less than 3% variation in electrical current supplied to the TFTEC module was seen between the experimental and modeling results. Based on the validated thermal model, a product use-condition modeling methodology was established in which the non-uniform heating of the product in use-condition was considered. This methodology was demonstrated using a product example and the hot spot temperature suppression was estimated to be 6/spl deg/C, compared to the case when no thermoelectric cooler was used. Several interesting phenomena such as creation of new hot spots around the TFTEC module region were also observed.

Sridhar Narasimhan

Papers

On-chip cooling by superlattice-based thin-film thermoelectrics

Soldering a die to a substrate

Microelectronic package and method for a compression-based mid-level interconnect

Feasibility study of using solid state refrigeration technologies for electronic cooling

Thin film thermoelectric cooler thermal validation and product thermal performance estimation