Learn the basic properties and designs of modern VLSI devices, as well as the factors affecting performance, with this thoroughly updated second edition. The first edition has been widely adopted as a standard textbook in microelectronics in many major US universities and worldwide. The internationally-renowned authors highlight the intricate interdependencies and subtle tradeoffs between various practically important device parameters, and also provide an in-depth discussion of device scaling and scaling limits of CMOS and bipolar devices. Equations and parameters provided are checked continuously against the reality of silicon data, making the book equally useful in practical transistor design and in the classroom. Every chapter has been updated to include the latest developments, such as MOSFET scale length theory, high-field transport model, and SiGe-base bipolar devices.

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Fundamentals of Modern VLSI Devices

We present an overview of negative bias temperature instability (NBTI) commonly observed in p-channel metal–oxide–semiconductor field-effect transistors when stressed with negative gate voltages at elevated temperatures. We discuss the results of such stress on device and circuit performance and review interface traps and oxide charges, their origin, present understanding, and changes due to NBTI. Next we discuss the effects of varying parameters (hydrogen, deuterium, nitrogen, nitride, water, fluorine, boron, gate material, holes, temperature, electric field, and gate length) on NBTI. We conclude with the present understanding of NBTI and its minimization.

Negative bias temperature instability: Road to cross in deep submicron silicon semiconductor manufacturing

Starting with a brief review on 0.1-/spl mu/m (100 nm) CMOS status, this paper addresses the key challenges in further scaling of CMOS technology into the nanometer (sub-100 nm) regime in light of fundamental physical effects and practical considerations. Among the issues discussed are: lithography, power supply and threshold voltage, short-channel effect, gate oxide, high-field effects, dopant number fluctuations and interconnect delays. The last part of the paper discusses several alternative or unconventional device structures, including silicon-on-insulator (SOI), SiGe MOSFET's, low-temperature CMOS, and double-gate MOSFET's, which may lead to the outermost limits of silicon scaling.

CMOS scaling into the nanometer regime

A predictive MOSFET model is critical for early circuit design research. To accurately predict the characteristics of nanoscale CMOS, emerging physical effects, such as process variations and correlations among model parameters, must be included. In this paper, a new generation of predictive technology model (PTM) is developed to accomplish this goal. Based on physical models and early-stage silicon data, the PTM of bulk CMOS is successfully generated for 130- to 32-nm technology nodes, with an Leff of as low as 13 nm. The accuracy of PTM predictions is comprehensively verified: The error of I on is below 10% for both n-channel MOS and p-channel MOS. By tuning only ten primary parameters, the PTM can be easily customized to cover a wide range of process uncertainties. Furthermore, the new PTM correctly captures process sensitivities in the nanometer regime, particularly the interactions among Leff, Vth, mobility, and saturation velocity. A website has been established for the release of PTM: http://www.eas.asu.edu/~ptm

New Generation of Predictive Technology Model for Sub-45 nm Early Design Exploration

https://engineering.purdue.edu/~ee650/downloads/NBTI-Ref1.pdf

A comprehensive model of PMOS NBTI degradation

A competitive 300-mm silicon photonics foundry technology has been developed by GLOBALFOUNDRIES for general availability, which takes advantage of advanced CMOS process technology and provides a manufacturing scale. A state-of-the-art process design kit offers a codesign environment with access to a comprehensive photonics device library along with a monolithically integrated SOI CMOS device library. Advances in automated wafer-level optical test enable statistical photonic device characterization for development, photonic modeling, and manufacturing controls. The key challenges and solutions in developing a manufacturable photonic technology with state-of-the-art performance are described, as well as a roadmap for next generation high-performance monolithic silicon photonics are outlined.

300-mm Monolithic Silicon Photonics Foundry Technology

Experimental results are presented on single-bit-upsets (SBU) and multiple-bit-upsets (MBU) on a 45 nm SOI SRAM. The accelerated testing results show the SBU-per-bit cross section is relatively constant with technology scaling but the MBU cross section is increasing. The MBU data show the importance of acquiring and analyzing the data with respect to the location of the multiple-bit upsets since the relative location of the cells is important in determining which MBU upsets can be corrected with error correcting code (ECC) circuits. For the SOI SRAMs, a large MBU orientation effect is observed with most of the MBU events occurring along the same SRAM bit-line; allowing ECC circuits to correct most of these MBU events.

Single-Event Upsets and Multiple-Bit Upsets on a 45 nm SOI SRAM

It is now well established that the negative bias temperature instability (NBTI) mechanism alters both the mean and variance of the distribution of the PFET under stress. This effect has reliability implications to balanced analog circuits (e.g., current mirrors, differential pairs, etc.), as well as to SRAM cell stability. This paper presents a brief review of the understanding and models to date of the statistics and impacts of the NBTI-induced variation. This is followed by a critical examination of the actual NBTI-induced distributions and the accuracy of the normal approximations that have been used to date.

Review and Reexamination of Reliability Effects Related to NBTI-Induced Statistical Variations

As negative-MOSFET (NMOSFET) size and voltage are scaled down, the electron-energy distribution becomes increasingly dependent only on the applied bias, because of quasi-ballistic transport over the high-field region. A new paradigm, or underlying concept, of NMOSFET hot-carrier behavior is proposed here, in which the fundamental "driving force" is available energy, rather than peak lateral electric field, as it is in the lucky electron model (LEM). The new prediction of the energy-driven paradigm is that the bias dependence of the impact-ionization (II) rate and hot-carrier lifetime is, to the first order, given by the energy dependences of the II scattering rate S/sub II/(E) and an effective interface state generation (ISG) cross section S/sub IT/(E), whereas, under the LEM, these bias dependences are determined by the number of electrons with energy above the II and ISG "threshold energies." This approach allows an experimental determination of S/sub IT/.

The energy-driven paradigm of NMOSFET hot-carrier effects

In this work the reliability of a 0.35 /spl mu/m p+ poly-gate pMOSFET CMOS technology under conductive channel hot carrier conditions is investigated. It is found that at any bias and temperature condition applied, the degradation of sufficiently short channel length (Leff/spl sime/0.14 um) devices results in a reduction in drive current due to the impact of donor type interface trap generation and positive charge formation during the stress. At these dimensions the degradation is controlled by a contribution of both Negative Bias Temperature Instability (NBTI) and Channel Hot Carrier (CHC) mechanism. We will show the role that each of these two mechanisms play in determining the shift of typical device parameters. A methodology to decouple the two effects is also provided allowing to quantify each contribution separately at any bias and temperature condition. A conductive CHC model that takes into account the impact of both mechanisms to the device lifetime at the worst observed degradation condition (Vg=Vd) is also discussed.

Stewart E. Rauch

Papers

300-mm Monolithic Silicon Photonics Foundry Technology

Single-Event Upsets and Multiple-Bit Upsets on a 45 nm SOI SRAM

Review and Reexamination of Reliability Effects Related to NBTI-Induced Statistical Variations

The energy-driven paradigm of NMOSFET hot-carrier effects

NBTI-channel hot carrier effects in PMOSFETs in advanced CMOS technologies