Showing papers in "IEEE Transactions on Device and Materials Reliability in 2005"
TL;DR: In this article, the authors review the types of failure modes for soft errors, the three dominant radiation mechanisms responsible for creating soft errors in terrestrial applications, and how these soft errors are generated by the collection of radiation-induced charge.
Abstract: The once-ephemeral radiation-induced soft error has become a key threat to advanced commercial electronic components and systems. Left unchallenged, soft errors have the potential for inducing the highest failure rate of all other reliability mechanisms combined. This article briefly reviews the types of failure modes for soft errors, the three dominant radiation mechanisms responsible for creating soft errors in terrestrial applications, and how these soft errors are generated by the collection of radiation-induced charge. The soft error sensitivity as a function of technology scaling for various memory and logic components is then presented with a consideration of which applications are most likely to require soft error mitigation.
1,345 citations
TL;DR: In this article, the authors review the status of reliability studies of high-k gate dielectrics and try to illustrate it with experimental results, showing that the reliability of Hf-based materials is influenced both by the interfacial layer as well as the high k layer.
Abstract: High-k gate dielectrics, particularly Hf-based materials, are likely to be implemented in CMOS advanced technologies. One of the important challenges in integrating these materials is to achieve lifetimes equal or better than their SiO/sub 2/ counterparts. In this paper we review the status of reliability studies of high-k gate dielectrics and try to illustrate it with experimental results. High-k materials show novel reliability phenomena related to the asymmetric gate band structure and the presence of fast and reversible charge. Reliability of high-k structures is influenced both by the interfacial layer as well as the high-k layer. One of the main issues is to understand these new mechanisms in order to asses the lifetime accurately and reduce them.
499 citations
TL;DR: Various SEU and SET mitigation schemes that could help the designer meet her or his goals are described.
Abstract: In nanometric technologies, circuits are increasingly sensitive to various kinds of perturbations. Soft errors, a concern for space applications in the past, became a reliability issue at ground level. Alpha particles and atmospheric neutrons induce single-event upsets (SEU), affecting memory cells, latches, and flip-flops, and single-event transients (SET), initiated in the combinational logic and captured by the latches and flip-flops associated to the outputs of this logic. To face this challenge, a designer must dispose a variety of soft error mitigation schemes adapted to various circuit structures, design architectures, and design constraints. In this paper, we describe various SEU and SET mitigation schemes that could help the designer meet her or his goals.
335 citations
TL;DR: An overview on the electrostatic discharge (ESD) protection circuits by using the silicon controlled rectifier (SCR)-based devices in CMOS ICs is presented and the solutions to overcome latchup issue in the SCR-based devices are discussed.
Abstract: An overview on the electrostatic discharge (ESD) protection circuits by using the silicon controlled rectifier (SCR)-based devices in CMOS ICs is presented The history and evolution of SCR device used for on-chip ESD protection is introduced Moreover, two practical problems (higher switching voltage and transient-induced latchup issue) limiting the use of SCR-based devices in on-chip ESD protection are reported Some modified device structures and trigger-assist circuit techniques to reduce the switching voltage of SCR-based devices are discussed The solutions to overcome latchup issue in the SCR-based devices are also discussed to safely apply the SCR-based devices for on-chip ESD protection in CMOS IC products
224 citations
TL;DR: In this paper, the authors present basic information about MRI interactions with implants with an emphasis on RF-induced heating of leads used for deep brain stimulation (DBS) used for DBS.
Abstract: There are three principal magnetic fields in magnetic resonance imaging (MRI) that may interact with medical implants. The static field will induce force and torque on ferromagnetic objects. The pulsed gradients are of audio frequency and the implant may concentrate the induced currents, with a potential for nerve stimulation or electrical inference. The currents induced in the body by the radio frequency (RF) field may also be concentrated by an implant, resulting in potentially dangerous heating of surrounding tissues. This paper presents basic information about MRI interactions with implants with an emphasis on RF-induced heating of leads used for deep brain stimulation (DBS). The temperature rise at the electrodes was measured in vitro as a function of the overall length of a DBS lead at an RF frequency of 64 MHz. The maximal temperature rise occurred for an overall length of 41 cm. The method of moments was used to calculate the current induced in the lead. From the induced currents, the RF power deposition near the electrodes was calculated and the heat equation was used to model the temperature rise. The calculated temperature rises as a function of lead length were in good agreement with the measured values.
222 citations
TL;DR: In this article, real-time experiments that evaluated large field programmable gate arrays (FPGAs) fabricated in different CMOS technologies (0.15 /spl mu/m, 0.13 /spl µ/m and 90 nm) for their sensitivity to radiation-induced single-event upsets (SEUs) were presented.
Abstract: Results are presented from real-time experiments that evaluated large field programmable gate arrays (FPGAs) fabricated in different CMOS technologies (0.15 /spl mu/m, 0.13 /spl mu/m, and 90 nm) for their sensitivity to radiation-induced single-event upsets (SEUs). These results are compared to circuit simulation (Qcrit) studies as well as to Los Alamos Neutron Science Center (LANSCE) neutron beam results and Crocker Nuclear Laboratory (University of California, Davis) cyclotron proton beam results.
216 citations
IBM1
TL;DR: In this paper, the authors review various causes of threshold voltage instability in high/spl kappa/ gate dielectric stacks, including charge trapping under positive bias stressing, positive charge creation under negative bias stressing (NBTI), hot-carrier stressing, de-trapping and transient charge trapping effects.
Abstract: Over recent years, there has been increasing research and development efforts to replace SiO/sub 2/ with high dielectric constant (high-/spl kappa/) materials such as HfO/sub 2/, HfSiO, and Al/sub 2/O/sub 3/. An important transistor reliability issue is the threshold voltage stability under prolonged stressing. In these materials, threshold voltage is observed to shift with stressing time and conditions, thereby giving rise to threshold voltage instabilities. In this paper, we review various causes of threshold voltage instability: charge trapping under positive bias stressing, positive charge creation under negative bias stressing (NBTI), hot-carrier stressing, de-trapping and transient charge trapping effects in high-/spl kappa/ gate dielectric stacks. Experimental and modeling studies for these threshold voltage instabilities are reviewed.
208 citations
TL;DR: In most system applications, a combination of several techniques is required to meet the necessary reliability and data-integrity targets, and the tradeoffs of these techniques in terms of area, power, and performance penalties versus increased reliability are covered.
Abstract: As the size of the SRAM cache and DRAM memory grows in servers and workstations, cosmic-ray errors are becoming a major concern for systems designers and end users. Several techniques exist to detect and mitigate the occurrence of cosmic-ray upset, such as error detection, error correction, cache scrubbing, and array interleaving. This paper covers the tradeoffs of these techniques in terms of area, power, and performance penalties versus increased reliability. In most system applications, a combination of several techniques is required to meet the necessary reliability and data-integrity targets.
205 citations
TL;DR: In this article, a series of experiments was undertaken at the Los Alamos Neutron Science Center (LANSCE) to ascertain whether fatal soft errors were indeed the primary cause of the elevated rate of single-node failures.
Abstract: Early in the deployment of the Advanced Simulation and Computing (ASC) Q supercomputer, a higher-than-expected number of single-node failures was observed. The elevated rate of single-node failures was hypothesized to be caused primarily by fatal soft errors, i.e., board-level cache (B-cache) tag (BTAG) parity errors caused by cosmic-ray-induced neutrons that led to node crashes. A series of experiments was undertaken at the Los Alamos Neutron Science Center (LANSCE) to ascertain whether fatal soft errors were indeed the primary cause of the elevated rate of single-node failures. Observed failure data from Q are consistent with the results from some of these experiments. Mitigation strategies have been developed, and scientists successfully use Q for large computations in the presence of fatal soft errors and other single-node failures.
160 citations
TL;DR: In this article, the potential for integrating ferroelectric polymer Langmuir-Blodgett (LB) films with semiconductor technology to produce NV-FRAM or NV-FeRAM and data-storage devices is discussed.
Abstract: We review the potential for integrating ferroelectric polymer Langmuir-Blodgett (LB) films with semiconductor technology to produce nonvolatile ferroelectric random-access memory (NV-FRAM or NV-FeRAM) and data-storage devices. The prototype material is a copolymer consisting of 70% vinylidene fluoride (VDF) and 30% trifluoroethylene (TrFE), or P(VDF-TrFE 70:30). Recent work with LB films and more conventional solvent-formed films shows that the VDF copolymers are promising materials for nonvolatile memory applications. The prototype device is the metal-ferroelectric-insulator-semiconductor (MFIS) capacitance memory. Field-effect transistor (FET)-based devices are also discussed. The LB films afford devices with low-voltage operation, but there are two important technical hurdles that must be surmounted. First, an appropriate method must be found to control switching dynamics in the LB copolymer films. Second, the LB technology must be scaled up and incorporated into the semiconductor-manufacturing process, but since there is no precedent for mass production of LB films, it is difficult to project how long this will take.
152 citations
TL;DR: Examples of the application of physics-based SEE simulations are presented, including scaling trends in soft error sensitivity as predicted by device simulation, single-event latchup (SEL) simulations in CMOS structures, and recent simulations of single- event transient production and propagation in digital logic circuits.
Abstract: This paper reviews techniques for physics-based device-level simulation of single-event effects (SEEs) in Si microelectronic devices and integrated circuits. Issues for device modeling of SEE are discussed in the context of providing physical insight into mechanisms contributing to SEE as well as providing predictive capabilities for calculation of SEE rates. Recent advances in device simulation methodology are detailed, including full-cell simulations and cross-section calculations from first principles. Examples of the application of physics-based SEE simulations are presented, including scaling trends in soft error sensitivity as predicted by device simulation, single-event latchup (SEL) simulations in CMOS structures, and recent simulations of single-event transient (SET) production and propagation in digital logic circuits.
TL;DR: In this paper, a review of considerations necessary for the prediction of soft error rates (SERs) for microprocessor designs is given, and the impact of logical and architectural filtering on SER calculations is discussed.
Abstract: This paper gives a review of considerations necessary for the prediction of soft error rates (SERs) for microprocessor designs. It summarizes the physics and silicon process dependencies of soft error mechanisms and describes the determination of SERs for basic circuit types. It reviews the impact of logical and architectural filtering on SER calculations and focuses on the structural filtering of soft radiation events by nodal timing mechanisms.
IBM1
TL;DR: In this paper, a new paradigm of NMOSFET hot-carrier behavior is proposed, in which the fundamental driving force is available energy, rather than peak lateral electric field, as it is in the lucky electron model (LEM).
Abstract: As negative-MOSFET (NMOSFET) size and voltage are scaled down, the electron-energy distribution becomes increasingly dependent only on the applied bias, because of quasi-ballistic transport over the high-field region. A new paradigm, or underlying concept, of NMOSFET hot-carrier behavior is proposed here, in which the fundamental "driving force" is available energy, rather than peak lateral electric field, as it is in the lucky electron model (LEM). The new prediction of the energy-driven paradigm is that the bias dependence of the impact-ionization (II) rate and hot-carrier lifetime is, to the first order, given by the energy dependences of the II scattering rate S/sub II/(E) and an effective interface state generation (ISG) cross section S/sub IT/(E), whereas, under the LEM, these bias dependences are determined by the number of electrons with energy above the II and ISG "threshold energies." This approach allows an experimental determination of S/sub IT/.
IBM1
TL;DR: The error detection and recovery within the z990 processors and the "nest" chips is described with respect to the system level protection against soft errors.
Abstract: Soft errors in logic are becoming more significant in the design of computer systems due to increased sensitivities of latches and combinatorial logic and the increased number of transistors on a chip At the same time, users of computer systems continue to expect higher levels of system reliability Therefore, the investment in hardware and firmware software mitigation is likely to continue to rise The IBM eServer z990 system is designed to detect and recover from myriad instances of soft and permanent errors The error detection and recovery within the z990 processors and the "nest" chips is described with respect to the system level protection against soft errors
TL;DR: In this paper, a diode-triggered silicon-controlled rectifier (DTSCR) was introduced for low-voltage application (signal and supply voltages /spl les/ 1.8 V) with extremely narrow ESD design margins.
Abstract: A novel diode-triggered silicon-controlled rectifier (DTSCR) (Mergens et al., 2003) electrostatic discharge (ESD) protection element is introduced for low-voltage application (signal and supply voltages /spl les/ 1.8 V) with extremely narrow ESD design margins. Trigger-voltage engineering in conjunction with fast and efficient SCR voltage clamping is applied for the protection of ultrasensitive circuit nodes, such as SiGe heterojunction bipolar transistor (HBT) base regions (e.g., f/sub Tmax/=45 GHz in BiCMOS 0.35-/spl mu/m LNA input) and thin gate oxides (e.g., t/sub ox/=1.7 nm in CMOS 0.09-/spl mu/m high-speed input). Ultrathin gate protection requires a reinforced trigger diode chain to avoid SCR trigger-speed issues resulting in critical trigger-voltage overshoots for very fast ESD transients such as a charged device model (CDM). SCR integration can be realized based on parasitic n-p-n/p-n-p inherent to CMOS devices or can alternatively be implemented based on vertical high-speed SiGe HBT with adjacent p+ SCR anode.
TL;DR: In this article, the soft error rate (SER) mitigations with standard process modifications in up-to-date commercial CMOS SRAMs and flip-flops are evaluated.
Abstract: This paper reviews soft error rate (SER) mitigations with standard process modifications in up-to-date commercial CMOS SRAMs and flip-flops. Acting in the front-end or middle-end levels, the following technology options are mainly evaluated: well engineering, partially and fully depleted silicon-on-insulator (FD SOI), and MIM capacitors. SER robustness gains are compared for eight classical process options based on original and published data. The best hardening efficiencies for SRAMs arise from the addition of stacked capacitors and the use of partially depleted (PD) SOI. SER trends are also reported for FD SOI and dual gates.
IBM1
TL;DR: In this article, it was shown that the cohesive energy of the interface is directly related to the activation energy for diffusion, and that the adhesion at the interface where mass transport is primarily taking place is related to electromigration flux.
Abstract: It has been demonstrated that, in those instances where electromigration-induced mass transport is dominated by interfacial diffusion, the adhesion at the interface where mass transport is primarily taking place is related to the electromigration flux. Furthermore, it is shown that the cohesive energy of the interface is directly related to the activation energy for diffusion.
TL;DR: This paper describes the steps necessary to develop a soft- error methodology that can be used at the circuit-simulation level for accurate nominal soft-error prediction.
Abstract: This paper describes the steps necessary to develop a soft-error methodology that can be used at the circuit-simulation level for accurate nominal soft-error prediction. It addresses the role of device simulations, statistical simulation, analytical soft-error rate (SER) model development, and SER-model calibration. The resulting approach is easily automated and generic enough to be applied to any type of circuit for estimation of the nominal SER.
TL;DR: In this paper, the authors used X-ray absorption spectroscopy (XAS) to study band edge electronic structure of high/spl kappa/ transition metal (TM) and trivalent lanthanide rare earth (RE) oxide gate dielectrics.
Abstract: X-ray absorption spectroscopy (XAS) is used to study band edge electronic structure of high-/spl kappa/ transition metal (TM) and trivalent lanthanide rare earth (RE) oxide gate dielectrics. The lowest conduction band d/sup */-states in TiO/sub 2/, ZrO/sub 2/ and HfO/sub 2/ are correlated with: 1) features in the O K/sub 1/ edge, and 2) transitions from occupied Ti 2p, Zr 3p and Hf 4p states to empty Ti 3d-, Zr 4d-, and Hf 5d-states, respectively. The relative energies of d-state features indicate that the respective optical bandgaps, E/sub opt/ (or equivalently, E/sub g/), and conduction band offset energy with respect to Si, E/sub B/, scale monotonically with the d-state energies of the TM/RE atoms. The multiplicity of d-state features in the Ti L/sub 2,3/ spectrum of TiO/sub 2/, and in the derivative of the O K/sub 1/ spectra for ZrO/sub 2/ and HfO/sub 2/ indicate a removal of d-state degeneracies that results from a static Jahn-Teller effect in these nanocrystalline thin film oxides. Similar removals of d-state degeneracies are demonstrated for complex TM/RE oxides including Zr and Hf titanates, and La, Gd and Dy scandates. Analysis of XAS and band edge spectra indicate an additional band edge state that is assigned Jahn-Teller distortions at internal grain boundaries. These band edges defect states are electronically active in photoconductivity (PC), internal photoemission (IPE), and act as bulk traps in metal oxide semiconductor (MOS) devices, contributing to asymmetries in tunneling and Frenkel-Poole transport that have important consequences for performance and reliability in advanced Si devices.
TL;DR: In this article, GaN-based light emitting diodes (LEDs) with p-cap layers grown at various temperatures were fabricated, and it was found that the LED with 900/spl deg/C-grown p-Cap layer could only endure negative 1100 V electrostatic discharge (ESD) pulses while the LEDs with 1040/spl dc deg/c-grown P-cap layer could endure ESD pulses as high as negative 3500 V.
Abstract: GaN-based light emitting diodes (LEDs) with p-cap layers grown at various temperatures were fabricated. It was found that the LED with 900/spl deg/C-grown p-cap layer could only endure negative 1100 V electrostatic discharge (ESD) pulses while the LED with 1040/spl deg/C-grown p-cap layer could endure ESD pulses as high as negative 3500 V. It was also found that the ESD performances of the LEDs with 900 and 1040/spl deg/C-grown p-cap layers were limited by the V-shape defects and the bonding pad design, respectively.
TL;DR: In this paper, the authors focus on power management and budgeting within the integrated circuits (ICs) to key system-design parameters, including power management, power-efficient memory design, weak-inversion analog design and test visibility.
Abstract: Implantable medical electronics are differentiated from most of the other electronic-system implementations by their unique combination of extreme low-power and high-reliability requirements. Many implanted medical devices rely on a fixed nonrechargeable battery over their entire lifetime. These constraints elevate power management and budgeting within the integrated circuits (ICs) to key system-design parameters. So much so, in fact, that the requirements drive not only differences in circuit design, but also place a number of constraints on the design environment and design tools, manufacturing processes, and targets used to implement those designs, test methodologies, and the fundamental understanding into the physics of failure. These constraints often make standard offerings available from the wafer foundries, electronic-design-automation (EDA) suppliers, and commercial third-party IP providers unviable without some level of modification. A successful design often requires process changes and monitoring to ensure low-static-current drain, digital-cell-library optimization with synthesis tools for low-power power-efficient memory design, weak-inversion analog design, accurate low-power models, and test visibility. As system complexity and activity rise, without a proportional increase in available energy, these challenges grow more persistent.
TL;DR: In this article, the authors performed a finite element analysis on line/via structures in two level Cu dual damascene interconnection system and found that the wide line and via fails earlier than the narrow line and/or via.
Abstract: Reliability of interconnect via is increasing an important issue in submicron technology. Electromigration experiments are performed on line/via structures in two level Cu dual damascene interconnection system and it is found that wide line/via fails earlier than the narrow line/via. Atomic flux divergence based finite element analyses is performed and stress-migration is found to be important in the failure rate behavior observed. Semi-classical width dependence Black's equation together with the finite element analysis revealed that the difference in the time to failure is due to the much larger average current density along the interface between the line and via for the wide line/via structure, and good agreement is obtained between the simulation and experimental results.
TL;DR: In this article, a novel technique to probe traps in ultrathin gate dielectrics, inelastic electron tunneling spectroscopy (IETS), was shown to be capable of revealing the energies and locations of traps in high/spl kappa/gate dielectric.
Abstract: Several special reliability features for Hf-based high-/spl kappa/ gate dielectrics are highlighted, including: 1) trapping-induced threshold voltage (V/sub th/) shift is much more of a concern than TDDB in determining the operating lifetime; 2) n-channel MOSFETs (nMOSFETs) are more vulnerable than p-channel MOSFETs (pMOSFETs); and 3) MOSFETs with polySi gates are more vulnerable than those with metal gates. These will be discussed in the context of existing electron/hole traps and trap generation by high-field stress. A novel technique to probe traps in ultrathin gate dielectrics, inelastic electron tunneling spectroscopy (IETS), will be shown to be capable of revealing the energies and locations of traps in high-/spl kappa/ gate dielectrics.
TL;DR: In this article, the impact of radio frequency (RF) and DC stress on passivated and unpassivated AlGaN/GaN modulation-doped field effect transistors (MODFETs) was investigated by means of DC and low-frequency noise (LFN) measurements.
Abstract: The impact of radio frequency (RF) and DC stress on passivated and unpassivated AlGaN/GaN modulation-doped field effect transistors (MODFETs) is investigated by means of DC and low-frequency noise (LFN) measurements. Unpassivated devices endure significant changes in the output resistance, gate, and drain noise current level after RF and DC stress. RF and DC stress of unpassivated devices leads to different degradation time constant and gate noise current. Besides, a positive shift in the pinch-off voltage is found to take place only after RF stress. In contrast to unpassivated devices, passivated devices do not show any considerable variation in the output resistance and gate, and drain noise current characteristics upon RF or DC stress. However, a positive shift in the pinch-off voltage upon RF stress is observed for both types of devices.
TL;DR: The undesirable production of secondary neutrons by cancer-radiotherapy linear accelerators (linac) has been demonstrated to cause soft errors in nearby electronics through the /sup 10/B(n,a)/sup 7/Li reaction as discussed by the authors.
Abstract: The undesirable production of secondary neutrons by cancer-radiotherapy linear accelerators (linac) has been demonstrated to cause soft errors in nearby electronics through the /sup 10/B(n,a)/sup 7/Li reaction. /sup 10/B is a component in the BPSG used as a dielectric material in some integrated-circuit (IC) fabrication processes.
TL;DR: In this paper, the authors review high/spl kappa/ materials specific phenomena that can affect the validity of constant-voltage-stress-based reliability test methods to address the direction of future reliability study on high-/spl Kappa/ devices.
Abstract: Charge trapping in high-/spl kappa/ gate dielectrics affects the result of electrical characterization significantly. DC mobility degradation and device threshold voltage instability and C-V and I-V hysteresis are a few examples. The charging effects in high-/spl kappa/ gate dielectric also affect the validity of conventional reliability test methodologies developed for SiO/sub 2/ devices. In this paper, we review high-/spl kappa/ materials specific phenomena that can affect the validity of constant-voltage-stress-based reliability test methods to address the direction of future reliability study on high-/spl kappa/ devices.
TL;DR: In this paper, the effect of high current on device performance was investigated using a Weibull-based statistical description with the objective of estimating the mean time to failure (MTTF) of devices during DC current stress.
Abstract: Gallium-nitride-based light-emitting diode (LED) accelerated life tests were carried out over devices adopting two different packaging schemes (i.e., with plastic transparent encapsulation or with pure metallic package). Data analyses were done using a Weibull-based statistical description with the aim of estimating the effect of high current on device performance. A consistent statistical model was found with the capability to estimate the mean time to failure (MTTF) of devices during DC current stress and the accelerating factors of high current stresses.
Abstract: This paper presents calculations of the electrical energy levels of the main point defects in ZrO/sub 2/, the oxygen vacancy and the oxygen interstitial. The levels are aligned to those of the Si channel using the known band offsets. The oxygen vacancy gives an energy level in the Si gap or just above the gap, depending on its charge state. This is the main electrically active defect and trap in ZrO/sub 2/ films. The oxygen interstitial gives levels just above the oxide valence band, and the neutral interstitial also gives a level near the Si conduction band.
TL;DR: In this article, the effects of direct current (dc) hot-carrier stress on the characteristics of NMOSFETs and a fully integrated low-noise amplifier (LNA) in an 0.18/spl mu/m complementary MOS (CMOS) technology are investigated.
Abstract: The effects of direct current (dc) hot-carrier stress on the characteristics of NMOSFETs and a fully integrated low-noise amplifier (LNA) made of NMOSFETs in an 0.18-/spl mu/m complementary MOS (CMOS) technology are investigated. The increase in threshold voltage and decrease in mobility caused by hot carriers lead to a drop in the biasing current of the transistors. These effects lead to a decrease in the transconductance and an increase of the output conductance of the device. No measurable change in the parasitic gate-source and gate-drain capacitances in the devices under test were observed due to hot carriers. In the LNA, the important effects caused by hot carriers were a drop of the power gain and an increase of the noise figure. A slight increase in the input and output matching S/sub 11/ and S/sub 22/, respectively, after hot-carrier stress was observed. The linearity parameter IIP3 of the LNA improved after stress. This is believed to be due to the improvement of the linearity of the I-V characteristics of the transistors in the LNA at the particular operating point where the measurements were performed.
TL;DR: In this paper, the authors determined that the total threshold voltage shift during a hot carrier stress is a sum of contributions from both hot carrier and cold carrier effects, and the contribution from the cold carrier can be evaluated by applying a de-trapping bias after the stress.
Abstract: Hot carrier reliability of the HfSiON dielectric with the TiN metal gate electrode has been studied in the nMOS and pMOS short channel transistors. Hot carrier induced degradation of the high-/spl kappa/ gate stack devices are severe than the one in the SiO/sub 2//poly devices. It is determined that total threshold voltage shift during a hot carrier stress is a sum of contributions from both hot carrier and cold carrier effects. The hot carrier contribution induces permanent damage while cold carrier contribution is shown to be reversible. The contribution from the cold carrier can be evaluated by applying a de-trapping (opposite polarity) bias after the stress.