S
Sweta Chander
Researcher at Indian Institute of Technology (BHU) Varanasi
Publications - 60
Citations - 518
Sweta Chander is an academic researcher from Indian Institute of Technology (BHU) Varanasi. The author has contributed to research in topics: Tunnel field-effect transistor & Field-effect transistor. The author has an hindex of 9, co-authored 44 publications receiving 293 citations. Previous affiliations of Sweta Chander include Lovely Professional University & Indian Institutes of Technology.
Papers
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Device and Circuit-Level Assessment of GaSb/Si Heterojunction Vertical Tunnel-FET for Low-Power Applications
Manas Ranjan Tripathy,Ashish Kumar Singh,A Samad,Sweta Chander,Kamalaksha Baral,Prince Kumar Singh,Satyabrata Jit +6 more
TL;DR: In this article, the performance of a vertically grown GaSb/Si tunnel field effect transistor (V-TFET) with a source pocket was investigated for the first time to enhance the carrier tunneling through the source-channel (Si) heterojunction.
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2-D Analytical Drain Current Model of Double-Gate Heterojunction TFETs With a SiO 2 /HfO 2 Stacked Gate-Oxide Structure
Sanjay Kumar,Kunal Singh,Sweta Chander,Ekta Goel,Prince Kumar Singh,Kamalaksha Baral,Balraj Singh,Satyabrata Jit +7 more
TL;DR: In this paper, a continuous 2D analytical drain current model of double-gate (DG) heterojunction tunnel field effect transistors (HJTFETs) with a SiO2/HfO2 stacked gate-oxide structures is presented.
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Heterojunction fully depleted SOI-TFET with oxide/source overlap
TL;DR: In this article, a hetero-junction fully depleted (FD) tunnel field effect transistor (TFET) nanostructure with oxide overlap on the Germanium-source region is proposed.
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Temperature analysis of Ge/Si heterojunction SOI-Tunnel FET
Sweta Chander,Sanjeet Kumar Sinha,Sanjay Kumar,Prince Kumar Singh,Kamalaksha Baral,Kunal Singh,S. Jit +6 more
TL;DR: In this paper, the impact of temperature variation on the electrical characteristics such as tunneling width, subthreshold swing, threshold voltage, and I O N / I O F F ratio of Ge/Si heterojunction tunnel field effect transistor (TFET) for different drain voltages was presented.
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A Two-Dimensional Gate Threshold Voltage Model for a Heterojunction SOI-Tunnel FET With Oxide/Source Overlap
Sweta Chander,Srimanta Baishya +1 more
TL;DR: In this article, a two-dimensional analytical gate threshold voltage model for a heterojunction silicon-on-insulator tunnel field effect transistor structure with gate oxide overlap is developed, where the infinite series method with suitable boundary conditions is used to solve the 2D Poisson's equation for surface potential.