T
T. Chalvatzis
Researcher at University of Toronto
Publications - 12
Citations - 610
T. Chalvatzis is an academic researcher from University of Toronto. The author has contributed to research in topics: CMOS & BiCMOS. The author has an hindex of 10, co-authored 12 publications receiving 596 citations.
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Proceedings Article
The invariance of characteristic current densities in nanoscale MOSFETs and its impact on algorithmic design methodologies and design porting of Si(Ge) (Bi)CMOS high-speed building blocks
Timothy O. Dickson,K.H.K. Yau,T. Chalvatzis,A. Mangan,E. Laskin,R. Beerkens,P. Westergaard,M. Tazlauanu,Ming-Ta Yang,Sorin P. Voinigescu +9 more
TL;DR: Evidence is provided that, as a result of constant-field scaling, the peak fT, peak fMAX, and optimum noise figure NFMIN current densities of Si and SOI n-channel MOSFETs are largely unchanged over technology nodes and foundries, and constant current-density biasing schemes are proposed to be applied to M OSFET analog/mixed-signal/RF and high-speed digital circuit design.
Journal ArticleDOI
The Invariance of Characteristic Current Densities in Nanoscale MOSFETs and Its Impact on Algorithmic Design Methodologies and Design Porting of Si(Ge) (Bi)CMOS High-Speed Building Blocks
Timothy O. Dickson,K.H.K. Yau,T. Chalvatzis,A. Mangan,E. Laskin,R. Beerkens,P. Westergaard,M. Tazlauanu,Ming-Ta Yang,Sorin P. Voinigescu +9 more
TL;DR: In this article, it was shown that the current densities of Si and SOI n-channel MOSFETs are largely unchanged over technology nodes and foundries, and that the characteristic current density also remains invariant for the most common circuit topologies such as MOS-SiGe HBT cascodes, MOS CML gates, and nMOS transimpedance amplifiers (TIAs) with active pMOS FET loads.
Journal ArticleDOI
A Low-Noise 40-GS/s Continuous-Time Bandpass $\Delta\Sigma$ ADC Centered at 2 GHz for Direct Sampling Receivers
TL;DR: A 40-GS/s continuous-time bandpass DeltaSigma analog-to-digital converter centered at 2 GHz for wireless base station applications and is designed entirely in the s-domain.
Journal ArticleDOI
Low-Voltage Topologies for 40-Gb/s Circuits in Nanoscale CMOS
TL;DR: In this article, a retiming flip-flop implemented in two different 90-nm and 65-nm CMOS technologies employs a MOS-CML Master-Slave latch topology with only two vertically stacked transistors.
Proceedings Article
Low-voltage topologies for 40-Gb/s circuits in nanoscale CMOS
TL;DR: In this paper, a retiming flip-flop implemented in two different 90-nm and 65-nm CMOS technologies employs a MOS-CML Master-Slave latch topology with only two vertically stacked transistors.