Spin-transfer torque RAM technology: Review and prospect

With the fast development of the fifth-generation cellular network technology (5G), the future sensors and microelectromechanical systems (MEMS)/nanoelectromechanical systems (NEMS) are presenting a more and more critical role to provide information in our daily life. This review paper introduces the development trends and perspectives of the future sensors and MEMS/NEMS. Starting from the issues of the MEMS fabrication, we introduced typical MEMS sensors for their applications in the Internet of Things (IoTs), such as MEMS physical sensor, MEMS acoustic sensor, and MEMS gas sensor. Toward the trends in intelligence and less power consumption, MEMS components including MEMS/NEMS switch, piezoelectric micromachined ultrasonic transducer (PMUT), and MEMS energy harvesting were investigated to assist the future sensors, such as event-based or almost zero-power. Furthermore, MEMS rigid substrate toward NEMS flexible-based for flexibility and interface was discussed as another important development trend for next-generation wearable or multi-functional sensors. Around the issues about the big data and human-machine realization for human beings’ manipulation, artificial intelligence (AI) and virtual reality (VR) technologies were finally realized using sensor nodes and its wave identification as future trends for various scenarios.

Development Trends and Perspectives of Future Sensors and MEMS/NEMS.

In recent years there has been significant interest and growth in low-power wireless technologies beyond traditional consumer use cases into medical applications [1]. Previously a bastion for application specific wireless propriety protocols, the WBAN community has worked together to develop a communication standard IEEE802.15.6 optimised for low power devices in and around the human body offering the levels of QoS required for personal medical data. Additionally, the consumer electronic industry has migrated existing standardised wireless protocols such as Bluetooth to meet the demanding low energy yet robust needs of WBAN. This paper presents a transceiver chip for both IEEE802.15.6 Narrow-Band (NB) PHY draft [2] and Bluetooth Low Energy (LE) 4.0 standards as well as proprietary protocols. Multi-mode operation offers the best solution in terms of flexibility and interoperability between devices and networks, and the appropriate protocol can be chosen to optimise power consumption in numerous applications scenarios where data throughput varies dramatically; such as streaming multi-lead ECG or episodic temperature measurements. The chip operates in the 2.36GHz MBANs spectrum, specifically allocated for medical devices, and the worldwide 2.4GHz ISM band. A TX for the 780/868/915/950MHz licence-free bands in China, EU, North America and Japan respectively, is also included. The chip is architected and designed for 5mW peak active power dissipation for compatibility with 1V button cells, hence enabling small-form factor non-intrusive body worn applications.

A 1 V 5 mA Multimode IEEE 802.15.6/Bluetooth Low-Energy WBAN Transceiver for Biotelemetry Applications

The present invention is directed to perform fine low-voltage control without largely increasing the circuit layout area in a low-power consumption structure. In the case of shifting a region to a low-speed mode, a system controller outputs a request signal and an enable signal to a power switch controller and a low-power drive circuit, respectively, to turn off a power switch and to perform a control so that the voltage level of a virtual reference potential becomes about 0.2 V to about 0.3V. The region operates on voltages between a power supply voltage and a virtual reference potential, so that it is controlled in the low-speed mode.

Semiconductor Integrated Circuit Device

In this paper, a low-power, highly linear, integrated, active-RC filter exhibiting a reconfigurable transfer function (Chebyshev, Elliptic) and bandwidth (5 MHz, 10 MHz), is presented. The filter exploits digitally-controlled polysilicon resistor banks and a digital automatic tuning scheme to account for process and temperature variations. The operational amplifiers used are based on a new compensation technique that allows optimized high-frequency filter performance and minimized current consumption. A filter prototype has been fabricated in a 0.12-mum CMOS process, occupies 0.25 mm2 (tuning circuit included), and achieves an IIP3 of approximately +20 dBm, whereas its spurious free dynamic range (SFDR) reaches 73 dB. The dissipation of the filter core and the tuning circuit is 4.6 mW and 1.5 mW, respectively

A Low-Power Wideband Reconfigurable Integrated Active-RC Filter With 73 dB SFDR

Implemented in a 015/spl mu/m CMOS process, the spread-spectrum clock generator uses the fractional PLL controlled by a /spl Delta//spl Sigma/ modulator An adaptive level shifter is adopted for expanding the input range of the /spl Delta//spl Sigma/ modulator The 15GHz prototype achieves the peak spurious reduction level of 203dB and the random jitter of 81 ps in a 250-cycle averaging period

Spread-spectrum clock generator for serial ATA using fractional PLL controlled by /spl Delta//spl Sigma/ modulator with level shifter

This paper presents a fully integrated SAR ADC for GSM/WCDMA/LTE triple-mode transceiver (RFIC) with non-binary DAC structure and digital correction techniques. All blocks including input buffer, ADC core, bias, references and ADC logics are implemented in a single chip with a small die area of 0.044 mm $^{2}$ /0.066 mm $^{2}$ for ADC core and ADC logic. The proposed ADC does not require off-chip decoupling capacitor for reference voltage by employing charge-sharing topology. Reconfigurable structure is used for multi-mode operation by adjusting ADC speed and noise, where SNDR of 67.0 dB in GSM and 58.2 dB in WCDMA/LTE are achieved at the sampling frequencies of 52 MS/s and 80 MS/s, respectively.

A Fully Integrated SAR ADC Using Digital Correction Technique for Triple-Mode Mobile Transceiver

A novel automatic tuning method for RC filters is proposed for CMOS low-IF transceivers. The method is based on a digital-DLL-like technique and tunes the time constant of filters automatically. The tuning range and the tuning accuracy are analyzed theoretically. To verify the method, a sixth-order 2-MHz IF filter for Bluetooth and a tuning circuit were fabricated in 0.18-/spl mu/m CMOS. The tuning circuit occupying 0.066 mm/sup 2/ includes only a reference first-order filter, a comparator, and a simple digital circuit. The measurement result of the filter and the tuning circuit shows that the maximum /spl plusmn/28% time-constant variation can be tuned within /spl plusmn/5% accuracy, which is consistent with theoretical results.

Novel automatic tuning method of RC filters using a digital-DLL technique

The influence of a jitter of a sampling clock of an analog-to-digital converter is digitally corrected at low power consumption. The sampling clock of the analog-to-digital converter is generated by a phase locked loop (PLL) using a reference clock, which has a lower frequency and lower jitter than the sampling clock, as a source oscillation. A time-to-digital converter (TDC) converts a timing error at a timing where the sampling clock and the reference clock are synchronized with each other into a digital value. A timing error at a sampling timing where the reference clock is not present is generated by interpolating a detected timing error. Thus, a jitter value of the sampling clock at each sampling timing is obtained. A sampling voltage error is calculated from the jitter value and the output of the analog-to-digital converter is digitally corrected.

Analog-to-digital converter and wireless receiver

A capacitive MEMS accelerometer with superior features, namely low cost, low noise, and low-power consumption, for a large sensor network was developed. To achieve both low noise and low-power consumption, a sensor architecture with a unique perforated and electrode-separated mass structure was devised. The MEMS elements were fabricated by using silicon-on-insulator wafers with 60- $\mu \text{m}$ -thick device layer and 380- $\mu \text{m}$ -thick handle layer for providing mechanical and electrical features independently. Two layers of perforation (which penetrates through the inertial mass) were designed by finite-element simulation for low mechanical noise. This design makes it possible to fabricate the inertial mass by a deep reactive ion etching process and to seal the MEMS element by a low-cost getter-less commercial packaging. A separated-servo-mass architecture is implemented with differential amplifiers for low electrical noise and low-power consumption by isolating the pick-off nodes for signal detection and the servo nodes for servo control electrically while maintaining the mechanical rigidity of the entire mass. A single-axis accelerometer implemented with the MEMS element and readout circuits demonstrated excellent performance with a low noise floor of less than 30 nG/ $\surd $ Hz and a low-power consumption of 20 mW in a getter-less vacuum ceramic package.

Takashi Oshima

Papers

Spread-spectrum clock generator for serial ATA using fractional PLL controlled by /spl Delta//spl Sigma/ modulator with level shifter

A Fully Integrated SAR ADC Using Digital Correction Technique for Triple-Mode Mobile Transceiver

Novel automatic tuning method of RC filters using a digital-DLL technique

Analog-to-digital converter and wireless receiver

Capacitive MEMS Accelerometer With Perforated and Electrically Separated Mass Structure for Low Noise and Low Power