T
Tatsuo Higuchi
Researcher at Tohoku University
Publications - 13
Citations - 219
Tatsuo Higuchi is an academic researcher from Tohoku University. The author has contributed to research in topics: Very-large-scale integration & NMOS logic. The author has an hindex of 6, co-authored 13 publications receiving 218 citations.
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A 32*32-bit multiplier using multiple-valued MOS current-mode circuits
TL;DR: In this article, a 32*32-bit multiplier using multiple-valued current-mode circuits has been fabricated in 2- mu m CMOS technology, which is half that of the corresponding binary CMOS multiplier.
Journal ArticleDOI
Design and implementation of quaternary NMOS integrated circuits for pipelined image processing
TL;DR: A pattern-matching procedure for performing four-valued image processing based on cellular logic operation is proposed, allowing two different templates to be processed simultaneously in a pipelined manner, and a compact NMOS image-processing chip has been implemented.
Journal Article
Prospects of multiple-valued VLSI processors
Journal ArticleDOI
High-density quaternary logic array chip for knowledge information processing systems
Takahiro Hanyu,Tatsuo Higuchi +1 more
TL;DR: A high-density NMOS logic array chip based on quaternary logic implemented for high-speed parallel pattern matching in a knowledge information processing system is described and it is shown that the chip area for pattern matching is reduced by 30% compared with the corresponding binary logic array.