Showing papers by "Tetsu Tanaka published in 2006"

Three-Dimensional Integration Technology Based on Wafer Bonding With Vertical Buried Interconnections

Abstract: A three-dimensional (3-D) integration technology has been developed for the fabrication of a new 3-D shared-memory test chip. This 3-D technology is based on the wafer bonding and thinning method. Five key technologies for 3-D integration were developed, namely, the formation of vertical buried interconnections, metal microbump formations, stacked wafer thinning, wafer alignment, and wafer bonding. Deep trenches having a diameter of 2 mum and a depth of approximately 50 mum were formed in the silicon substrate using inductively coupled plasma etching to form vertical buried interconnections. These trenches were oxidized and filled with n+ polycrystalline silicon or tungsten. The 3-D devices and 3-D shared-memory test chips with three-stacked layers were fabricated by bonding the wafers with vertical buried interconnections after thinning. No characteristic degradation was observed in the fabricated 3-D devices. It was confirmed that fundamental memory operation and broadcast operation between the three memory layers could be successfully performed in the fabricated 3-D shared-memory test chip

A capacitorless 1T-DRAM technology using gate-induced drain-leakage (GIDL) current for low-power and high-speed embedded memory

Abstract: A capacitorless one-transistor (1T)-dynamic random-access memory (DRAM) cell using gate-induced drain-leakage (GIDL) current for write operation was demonstrated. Compared with the conventional write operation with impact-ionization (II) current, the write operation with GIDL current achieves power consumption that is lower by four orders of magnitude and a write speed within several nanoseconds. The capacitorless 1T DRAM is the most promising technology for high-performance embedded-DRAM large-scale integration.

Magnetic properties of FePt nanodots formed by a self-assembled nanodot deposition method

Abstract: Fe50Pt50 nanodots dispersed in a SiO2 film (Fe50Pt50 nanodot film) were formed by a self-assembled nanodot deposition (SAND) method in which Fe50Pt50 and SiO2 are cosputtered in a high vacuum rf magnetron sputtering equipment. Fe50Pt50 pellets are laid on a SiO2 target in a sputtering chamber to form the Fe50Pt50 nanodot film in the SAND method. The size and density of Fe50Pt50 nanodot were controlled by changing the ratio of the total area of Fe50Pt50 pellets to that of SiO2 target. The Fe50Pt50 nanodot size decreases and its density increases when the ratio decreases. As-deposited Fe50Pt50 nanodots self-assembled to a face-centered-cubic phase of single-crystal structure. The Fe50Pt50 nanodot films were annealed to evaluate the nanodot size controllability, the magnetic anisotropy, and the thermal stability. Fully ordered L10 face-centered-tetragonal Fe50Pt50 nanodots with high magnetocrystalline anisotropy (Ku≅8.7×107ergs∕cm3) were obtained by in situ annealing at 600°C for 1h in a high vacuum ambience...

Novel Retinal Prosthesis System with Three Dimensionally Stacked LSI Chip

Abstract: We have proposed a novel retinal prosthesis system with three-dimensionally stacked retinal prosthesis chip. The retinal prosthesis chip consists of several LSI chips that are vertically stacked and electrically connected using three-dimensional integration technology. We fabricated retinal prosthesis chip including photodetectors and stimulus current generators. We confirmed that current waveform parameters can be varied by bias voltages. Implantable stimulus electrode array was also fabricated for the electrical stimulation of the retina. To evaluate optimal retinal stimulus current, electrically evoked potential (EEP) was recorded in animal experiments. The recorded waveform shows a similar behavior to the visually evoked potential (VEP) waveform, indicating possibilities that the electrical stimulation of the retina can restore visual sensation for the blind patients.

New three-dimensional integration technology to achieve a super chip

Abstract: We have proposed a new three-dimensional (3D) integration technology based on a chip-to-wafer bonding method which is called a super chip integration technology. Various kinds of chips such as processor chip, memory chips, analog IC chip and sensor chips which are fabricated by different technologies can be vertically stacked into a 3D LSI chip by using a super chip integration technology. Such 3D LSI chip is called a super chip. Various kinds of chips with different chip size, chip thickness and material can be vertically stacked in the super chip integration technology. To establish the super chip integration technology, several key technologies of vertical interconnection formation, chip alignment and bonding, adhesive injection, and chip thinning and planarization were developed. By using the super chip integration technology, three-layer stacked LSI chips with vertical interconnections were successfully fabricated

Research and development of transistor structure in nano-scale region

Abstract: In this work, new silicon-on-low-k substrate (SOLK) MOSFET and germanium-on-low-k substrate (GOLK) MISFET are proposed. SOLK-MOSFET with metal back-gate was successfully fabricated using wafer bonding method with low-k material as an adhesive. It was shown that the threshold voltage, the on-current, and the off-current are more effectively controlled by the back-gate bias voltage in SOLK-MOSFETs with metal back-gate than in SOI-MOSFETs with buried back-gate. Ge MISFETs were fabricated with HfO2 gate dielectric and W/W2N metal gate which are formed on GOI wafer obtained by a new graded Ge condensation method. Excellent drain current-voltage characteristics and subthreshold characteristics in are obtained in the fabricated GOI-MISFETs.

New non-volatile memory with magnetic nano-dots

Abstract: We proposed a new non-volatile memory with magnetic nano-dots (MND) dispersed in an insulating film as charge retention layer. We evaluated fundamental characteristics of FePt magnetic nano-dot film which is employed in such new magnetic nano-dot memory. We successfully formed a highly ordered L1 0 phase face-centered tetragonal structured FePt nano-dot ( < 4.2nm) films on Si 3 N 4 (5nm)/SiO 2 (10nm)/silicon substrates and SiO 2 (10nm)/ silicon substrate by using SAND method. The uniformity of FePt particle size is dramatically improved by introducing a Si 3 N 4 buffer layer on SiO 2 /Si substrate. In addition, it is found that FePt nano-dot film formed on Si3N4(5nm)/Si02(10nm)/Si substrate has a large coerce-ivity of ∼22 kOe at room temperature.