There is, I think, something ethereal about i —the square root of minus one. I remember first hearing about it at school. It seemed an odd beast at that time—an intruder hovering on the edge of reality.

Usually familiarity dulls this sense of the bizarre, but in the case of i it was the reverse: over the years the sense of its surreal nature intensified. It seemed that it was impossible to write mathematics that described the real world in …

I and i

An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Semiconductor device, and manufacturing method thereof

Various embodiments for improved power devices as well as their methods of manufacture, packaging and circuitry incorporating the same for use in a wide variety of power electronic applications are disclosed. One aspect of the invention combines a number of charge balancing techniques and other techniques for reducing parasitic capacitance to arrive at different embodiments for power devices with improved voltage performance, higher switching speed, and lower on-resistance. Another aspect of the invention provides improved termination structures for low, medium and high voltage devices. Improved methods of fabrication for power devices are provided according to other aspects of the invention. Improvements to specific processing steps, such as formation of trenches, formation of dielectric layers inside trenches, formation of mesa structures and processes for reducing substrate thickness, among others, are presented. According to another aspect of the invention, charge balanced power devices incorporate temperature and current sensing elements such as diodes on the same die. Other aspects of the invention improve equivalent series resistance (ESR) for power devices, incorporate additional circuitry on the same chip as the power device and provide improvements to the packaging of charge balanced power devices.

Power semiconductor devices and methods of manufacture

A power semiconductor device includes trenches disposed in a first base layer of a first conductivity type at intervals to partition main and dummy cells, at a position remote from a collector layer of a second conductivity type. In the main cell, a second base layer of the second conductivity type, and an emitter layer of the first conductivity type are disposed. In the dummy cell, a buffer layer of the second conductivity type is disposed. A gate electrode is disposed, through a gate insulating film, in a trench adjacent to the main cell. A buffer resistor having an infinitely large resistance value is inserted between the buffer layer and emitter electrode. The dummy cell is provided with an inhibiting structure to reduce carriers of the second conductivity type to flow to and accumulate in the buffer layer from the collector layer.

Power semiconductor device

Recent success with the fabrication of high-performance GaN-on-Si high-voltage HFETs has made this technology a contender for power electronic applications. This paper discusses the properties of GaN that make it an attractive alternative to established silicon and emerging SiC power devices. Progress in development of vertical power devices from bulk GaN is reviewed followed by analysis of the prospects for GaN-on-Si HFET structures. Challenges and innovative solutions to creating enhancement-mode power switches are reviewed.

https://iopscience.iop.org/article/10.1088/0268-1242/28/7/074011/pdf

Gallium nitride devices for power electronic applications

PROBLEM TO BE SOLVED: To provide a field-effect transistor manufacturing method that utilizes diffusion of magnesium from a lower layer. SOLUTION: When epitaxial growth is performed so as to form a GaN layer without introducing an Mg material while covering a part of the surface of a p-type layer 1p with a mask layer 2m; a p-body layer 4p is formed at a part contacting with the p-type layer 1p of the lower layer due to dispersion of Mg from the p-type layer 1p, and a channel forming layer 4i composed of undoped GaN is formed in the upper part of the mask layer 2m. Similarly, a p-AlGaN layer 5p is formed in the upper part of the p-body layer 4p due to dispersion of Mg from the p-body layer 4p, and an undoped AlGaN layer 5i is formed in the upper part of the channel forming layer 4i. A HEMT 100 formed in such a manner as described above has excellent ohmic properties since the surface of the p-AlGaN layer 5p, on which a body electrode Bd is formed, is not subjected to etching processing and is capable of stably maintaining potential of the channel forming layer 4i from the body electrode Bd via the p-AlGaN layer 5p and the p-body layer 4p so as to become an element with stable element characteristics. COPYRIGHT: (C)2008,JPO&INPIT

Manufacturing method for group iii nitride-based compound semiconductor element

PROBLEM TO BE SOLVED: To suppress a leak current of a heterojunction type group III-V compound semiconductor device when the semiconductor device is turned off, and to reduce resistance when the device is turned on. SOLUTION: The group III-V compound semiconductor has a lower layer 46 of GaN, an upper layer 48 of AlGaN which has a heterojunction with the lower layer 46 and also has a band gap larger than a band gap of the lower layer 46, a source electrode 54 formed at a portion of the surface of the upper layer 48, and a gate electrode 52 formed at the other portion of the surface of the upper layer 48; and the lower layer 64 has a crystal defect high-density region 72 and a crystal defect low-density region distributed in a surface parallel to a heterojunction surface, the source electrode 54 is formed in a region opposed to the crystal defect low-density region, and the gate electrode 52 is formed in a region opposed to the crystal defect high-density region 72. COPYRIGHT: (C)2006,JPO&NCIPI

Heterojunction type group iii-v compound semiconductor device and its manufacturing method

The design, simulations and optimization of a novel high-voltage vertical GaN MOS-controlled High Electron Mobility Transistor (HEMT) with epitaxially grown thin p type body and terrace gate structure is presented, with projected maximum breakdown voltage of 1289 V, Ron,sp of 1.9 mΩ-cm2, and switching power loss of 34.9 μJ/cm2 and 2.60 μJ/cm2 for drain and gate respectively. (© 2010 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim)

Design and simulations of novel enhancement-mode high-voltage GaN vertical hybrid MOS-HEMTs

PROBLEM TO BE SOLVED: To prevent defective crystals at a surface corner part of a trench and chamfer the corner part of the trench in a substrate SOLUTION: A semiconductor substrate 10 is etched from an opening 32 of a mask film 30 to form a recessed part 34 in a forward tapered state A sidewall film 38 is formed selectively so as to cover a forward tapered region of the recessed part 34 The lower trench part 40 is dug with the mask of the sidewall film 38 in an anisotropic etching step A heat treatment step is carried out to form a sacrificial oxide film 42 on a trench surface, and the sacrificial oxide film 42 is removed to obtain a trench 44 When the trench is used as a trench gate, a gate-insulating film 46 is formed on the trench surface, and a doping amorphous silicon as an electrode material is doped, and a heat treatment is carried out at a temperature above 900 degC In this way, the deep trench is formed, while the forward tapered region is protected by the sidewall film so the first heat treatment can be carried out after the chamfering the surface corner part, and then defects in crystal are prevented

Manufacture for semiconductor device

A HEMT has a drain region adapted to be electrically connected to a high voltage of an electric source, a source region adapted to be electrically connected to a low voltage of the electric source. A first semiconductor region is disposed between the drain region and the source region. A MIS structure and a heterostructure are disposed at a surface of the first semiconductor region. The MIS structure includes a gate electrode that faces a portion of a surface of the first semiconductor region with a gate insulating membrane therebetween. The heterostructure includes a second semiconductor region which makes contact with a rest portion of the surface of the first semiconductor region and has a wider band-gap than the first semiconductor region. The drain region and the source region are capable of being electrically connected with a structure in which the MIS structure 40 and the heterostructure are arranged in series.

Tsutomu Uesugi

Papers

Manufacturing method for group iii nitride-based compound semiconductor element

Heterojunction type group iii-v compound semiconductor device and its manufacturing method

Design and simulations of novel enhancement-mode high-voltage GaN vertical hybrid MOS-HEMTs

Manufacture for semiconductor device

HEMT including MIS structure