There is, I think, something ethereal about i —the square root of minus one. I remember first hearing about it at school. It seemed an odd beast at that time—an intruder hovering on the edge of reality.

Usually familiarity dulls this sense of the bizarre, but in the case of i it was the reverse: over the years the sense of its surreal nature intensified. It seemed that it was impossible to write mathematics that described the real world in …

I and i

An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Semiconductor device, and manufacturing method thereof

Various embodiments for improved power devices as well as their methods of manufacture, packaging and circuitry incorporating the same for use in a wide variety of power electronic applications are disclosed. One aspect of the invention combines a number of charge balancing techniques and other techniques for reducing parasitic capacitance to arrive at different embodiments for power devices with improved voltage performance, higher switching speed, and lower on-resistance. Another aspect of the invention provides improved termination structures for low, medium and high voltage devices. Improved methods of fabrication for power devices are provided according to other aspects of the invention. Improvements to specific processing steps, such as formation of trenches, formation of dielectric layers inside trenches, formation of mesa structures and processes for reducing substrate thickness, among others, are presented. According to another aspect of the invention, charge balanced power devices incorporate temperature and current sensing elements such as diodes on the same die. Other aspects of the invention improve equivalent series resistance (ESR) for power devices, incorporate additional circuitry on the same chip as the power device and provide improvements to the packaging of charge balanced power devices.

Power semiconductor devices and methods of manufacture

A power semiconductor device includes trenches disposed in a first base layer of a first conductivity type at intervals to partition main and dummy cells, at a position remote from a collector layer of a second conductivity type. In the main cell, a second base layer of the second conductivity type, and an emitter layer of the first conductivity type are disposed. In the dummy cell, a buffer layer of the second conductivity type is disposed. A gate electrode is disposed, through a gate insulating film, in a trench adjacent to the main cell. A buffer resistor having an infinitely large resistance value is inserted between the buffer layer and emitter electrode. The dummy cell is provided with an inhibiting structure to reduce carriers of the second conductivity type to flow to and accumulate in the buffer layer from the collector layer.

Power semiconductor device

Recent success with the fabrication of high-performance GaN-on-Si high-voltage HFETs has made this technology a contender for power electronic applications. This paper discusses the properties of GaN that make it an attractive alternative to established silicon and emerging SiC power devices. Progress in development of vertical power devices from bulk GaN is reviewed followed by analysis of the prospects for GaN-on-Si HFET structures. Challenges and innovative solutions to creating enhancement-mode power switches are reviewed.

https://iopscience.iop.org/article/10.1088/0268-1242/28/7/074011/pdf

Gallium nitride devices for power electronic applications

PROBLEM TO BE SOLVED: To develop a technique capable of specifying the position of an electric field region for a short time, the electric field region being developed by current collapse caused in a hetero junction field effect transistor.SOLUTION: An evaluation device 100 for observing a current collapse phenomenon caused in a hetero junction field effect transistor 1 includes: a light irradiation device 10 for irradiating laser beams on the hetero junction field effect transistor 1; and a detection device 20 for detecting the strength of a secondary higher harmonic (SHG: Second Harmonic Generation) generated in a region irradiated with the laser beams.

Method and device for observing hetero junction field effect transistor phenomenon

PROBLEM TO BE SOLVED: To obtain a semiconductor layer of gallium nitride where cracks are hardly generated. SOLUTION: A method for manufacturing a semiconductor lamination comprises a first process for forming wall sections 22 that are extended in almost vertical directions from the surface of a silicon substrate 10 and comparts the surface of the substrate 10 into a plurality of regions, a second process for forming semiconductor layers 42 by performing crystal growth on gallium nitride of a semiconductor material different from that of the substrate 10 from each region on the surface of the substrate 10 comparted by the sections 22, and a third process for forming a plurality of semiconductor laminations by dicing the layers 42 along at least a part of planer patterns of the sections 22 and allowing the layers 42 to be laminated on the surface of the substrate 10. COPYRIGHT: (C)2007,JPO&INPIT

Method for manufacturing semiconductor lamination

We focus on reliability issues of gate oxides and $p-n$ junctions to realize vertical GaN metal-oxide-semiconductor field-effect transistors (MOSFETs). An annealed AlSiO gate oxide on GaN displayed a lifetime of over 20 years at 150 °C and suppressed positive bias instability in MOSFETs. The key to high channel mobility and stability under positive gate bias is the interface structure designed to minimize oxide border traps. We also evaluated the reliability of GaN p-n diodes (PNDs) on freestanding GaN substrates with different threading dislocation densities. The reverse leakage for PNDs involving threading dislocations was explained by variable-range hopping, while the reverse leakage for dislocation-free PNDs was dominated by band-to-band tunneling. The fabricated PNDs demonstrated excellent robustness under high-temperature reverse bias. However, after continuous forward current stress, reverse leakage pathways were formed at threading screw dislocations, which should be minimized in future GaN substrates.

Reliability issues of gate oxides and $p-n$ junctions for vertical GaN metal–oxide–semiconductor field-effect transistors (Invited)

PROBLEM TO BE SOLVED: To provide a laminated electrode with an improved adhesive property with a semiconductor layer at least on one surface of a group III nitride based semiconductor layer. SOLUTION: This laminated electrode forming method comprises: a first process, a second process and a third process. In the first process, a first metal film 38 composed of Mg or Cr is formed on the backside 82 of a semiconductor layer 80. In the second process, a second metal film 36 composed of Al is formed on the first metal film 38. In the third process, a third metal film 34 composed of Cu is formed on the second metal film 36. COPYRIGHT: (C)2010,JPO&INPIT

Laminated electrode forming method and semiconductor device equipped with laminated electrode

This work examined the intentional generation of recombination centers in GaN p– n junctions on freestanding GaN substrates. Irradiation with a 4.2 MeV proton beam was used to create a uniform distribution of vacancies and interstitials across GaN p+/ n− and p−/ n+ junctions through anode electrodes. With increasing proton dose, the effective doping concentrations were found to be reduced. Because the reduction in the doping concentration was much higher than the hydrogen atom concentration, this decrease could not be attributed solely to carrier compensation resulting from interstitial hydrogen atoms. In fact, more than half of the electron and hole compensation was caused by the presence of point defects. These defects evidently served as Shockley–Read–Hall (SRH) recombination centers such that the SRH lifetimes were reduced to several picoseconds from several hundred picoseconds prior to irradiation. The compensation for holes in the p−/ n+ junctions was almost double that for electrons in the p+/ n− junctions. Furthermore, the SRH lifetimes associated with p−/ n+ junctions were shorter than those for p+/ n− junctions for a given proton dose. These differences can be explained by variations in the charge state and/or the formation energy of intrinsic point defects in the p-type and n-type GaN layers. The results of the present work indicate the asymmetry of defect formation in GaN based on the fact that intrinsic point defects in p-type GaN readily compensate for holes.

Tsutomu Uesugi

Papers

Method and device for observing hetero junction field effect transistor phenomenon

Method for manufacturing semiconductor lamination

Reliability issues of gate oxides and $p-n$ junctions for vertical GaN metal–oxide–semiconductor field-effect transistors (Invited)

Laminated electrode forming method and semiconductor device equipped with laminated electrode

Effects of proton irradiation-induced point defects on Shockley–Read–Hall recombination lifetimes in homoepitaxial GaN p–n junctions