There is, I think, something ethereal about i —the square root of minus one. I remember first hearing about it at school. It seemed an odd beast at that time—an intruder hovering on the edge of reality.

Usually familiarity dulls this sense of the bizarre, but in the case of i it was the reverse: over the years the sense of its surreal nature intensified. It seemed that it was impossible to write mathematics that described the real world in …

I and i

An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Semiconductor device, and manufacturing method thereof

Various embodiments for improved power devices as well as their methods of manufacture, packaging and circuitry incorporating the same for use in a wide variety of power electronic applications are disclosed. One aspect of the invention combines a number of charge balancing techniques and other techniques for reducing parasitic capacitance to arrive at different embodiments for power devices with improved voltage performance, higher switching speed, and lower on-resistance. Another aspect of the invention provides improved termination structures for low, medium and high voltage devices. Improved methods of fabrication for power devices are provided according to other aspects of the invention. Improvements to specific processing steps, such as formation of trenches, formation of dielectric layers inside trenches, formation of mesa structures and processes for reducing substrate thickness, among others, are presented. According to another aspect of the invention, charge balanced power devices incorporate temperature and current sensing elements such as diodes on the same die. Other aspects of the invention improve equivalent series resistance (ESR) for power devices, incorporate additional circuitry on the same chip as the power device and provide improvements to the packaging of charge balanced power devices.

Power semiconductor devices and methods of manufacture

A power semiconductor device includes trenches disposed in a first base layer of a first conductivity type at intervals to partition main and dummy cells, at a position remote from a collector layer of a second conductivity type. In the main cell, a second base layer of the second conductivity type, and an emitter layer of the first conductivity type are disposed. In the dummy cell, a buffer layer of the second conductivity type is disposed. A gate electrode is disposed, through a gate insulating film, in a trench adjacent to the main cell. A buffer resistor having an infinitely large resistance value is inserted between the buffer layer and emitter electrode. The dummy cell is provided with an inhibiting structure to reduce carriers of the second conductivity type to flow to and accumulate in the buffer layer from the collector layer.

Power semiconductor device

Recent success with the fabrication of high-performance GaN-on-Si high-voltage HFETs has made this technology a contender for power electronic applications. This paper discusses the properties of GaN that make it an attractive alternative to established silicon and emerging SiC power devices. Progress in development of vertical power devices from bulk GaN is reviewed followed by analysis of the prospects for GaN-on-Si HFET structures. Challenges and innovative solutions to creating enhancement-mode power switches are reviewed.

https://iopscience.iop.org/article/10.1088/0268-1242/28/7/074011/pdf

Gallium nitride devices for power electronic applications

Herein, we propose and demonstrate the edge termination for GaN-based one-sided abrupt p–n junctions. The structure is comprised of a combination of a shallow negative bevel mesa and selective-area p-type doping under the mesa. Based on the Technology Computer Aided Design (TCAD) simulation, the maximum electric field at the junction edge is markedly reduced to approximately 1.3 times that of the parallel-plane electric field in the proposed structure, which is almost half of the unimplanted diode. The TCAD simulation also shows that the shallow mesa angle of 6 ° effectively reduces the optimum acceptor concentration (Na) in the implanted region and enhances the breakdown voltage. The optimum Na value can be covered by the proposed technology based on the Mg-ion implantation and subsequent ultra-high-pressure annealing (UHPA). Using the formation of the shallow bevel mesa, the Mg-ion implantation, and the UHPA process, we experimentally demonstrate the p–n diodes with a breakdown voltage over 600 V, which is in good agreement with the TCAD simulation. The proposed method can be applied to a vertical trench-gate metal-oxide-semiconductor field-effect transistor with a high figure-of-merit.

Mg-implanted bevel edge termination structure for GaN power device applications

The Shockley–Read-Hall (SRH) lifetime in homoepitaxial p-GaN (N a = 1 × 1017 cm−3) is investigated by analyzing forward current–voltage (I–V) characteristics in GaN-on-GaN p–n+ junction diodes with mesa-isolation structure. The ideality factor around 2 due to recombination current was obtained in the 1.8–2.7 V window, which is different from the characteristic of a p+-n− junction involving considerable diffusion current. The recombination current was proportional to the junction area, indicating that the recombination current is a bulk component, not a mesa-surface component. Analyzing the recombination current with consideration of the SRH recombination rate in the depletion layer, we obtained an SRH lifetime of 46 ps at 298 K. The temperature dependence of the I–V characteristics was also investigated and the SRH lifetimes were extracted in the range of 223–573 K. The SRH lifetime in homoepitaxial p-GaN followed the empirical power law of = 1.2 × 10−16 × T 2.25 (s).

https://iopscience.iop.org/article/10.7567/1347-4065/ab07ad/pdf

Shockley-Read-Hall lifetime in homoepitaxial p-GaN extracted from recombination current in GaN p-n + junction diodes

A vertical semiconductor device having an insulated gate structure makes use of a double-gate structure. The double-gate structure dramatically reduces the channel resistance, JFET resistance, and epitaxial resistance of the on-resistance of the power MOSFET, and implements an adequate breakdown voltage due to the effect of gate bias. In principle, a first gate and second gate having mutually facing portions are driven synchronously. This causes first and second channels to be formed in correspondence with first and second gates, and the currents flowing through these first and second channels form the on-current for this power device having a vertical structure.

Insulated gate semiconductor device and fabrication method therefor

Two-dimensional current collapse imaging of a Schottky gate AlGaN/GaN high electron mobility transistor device was achieved by optical electric field-induced second-harmonic generation (EFISHG) measurements. EFISHG measurements can detect the electric field produced by carriers trapped in the on-state of the device, which leads to current collapse. Immediately after (e.g., 1, 100, or 800 μs) the completion of drain-stress voltage (200 V) in the off-state, the second-harmonic (SH) signals appeared within 2 μm from the gate edge on the drain electrode. The SH signal intensity became weak with time, which suggests that the trapped carriers are emitted from the trap sites. The SH signal location supports the well-known virtual gate model for current collapse.

Current collapse imaging of Schottky gate AlGaN/GaN high electron mobility transistors by electric field-induced optical second-harmonic generation measurement

https://iopscience.iop.org/article/10.35848/1882-0786/ac0b09/pdf

Tsutomu Uesugi

Papers

Mg-implanted bevel edge termination structure for GaN power device applications

Shockley-Read-Hall lifetime in homoepitaxial p-GaN extracted from recombination current in GaN p-n + junction diodes

Insulated gate semiconductor device and fabrication method therefor

Current collapse imaging of Schottky gate AlGaN/GaN high electron mobility transistors by electric field-induced optical second-harmonic generation measurement

Design and demonstration of nearly-ideal edge termination for GaN p–n junction using Mg-implanted field limiting rings