As foreseen by Keyes in the late 1960s, the self-heating effect has emerged as an important concern for device performance, output power density, run-time variability, and reliability of modern field-effect transistors. The self-heating effect is aggravated as the device footprint scales down for higher level of integration (low-power devices) or as the devices are operated in ultrahigh voltage regimes (high-power devices). In this article, we focus on the implications of self-heating on hot carrier degradation (HCD) of modern transistors by integrating within a coherent theoretical framework a broad range of experimental data scattered in the literature. We explain why system integration exacerbates transistor self-heating, while high-frequency digital operation ameliorates it, suggesting an opportunity for co-optimization. We conclude this article by discussing the various material–device–system design strategies to reduce HCD and suggesting open problems for further research.

A Device-to-System Perspective Regarding Self-Heating Enhanced Hot Carrier Degradation in Modern Field-Effect Transistors: A Topical Review

In advanced technology nodes, an increase in power density, use of nonplanar architectures, and novel materials can aggravate local self-heating due to active power dissipation. In this paper, 3-D device simulations are performed to analyze thermal effects in fin-shaped field-effect transistors (FinFETs) and stacked-nanowire FETs (NWFETs). Based on empirically extracted equations, a new model for thermal resistance estimation is proposed, which for the first time takes into account the aggregate impact of a number of fins, number of gate fingers, number, and dimensions of stacked nanowires. We have extracted the proposed model against calibrated 3-D TCAD simulations over a range of device design variables of interest. Our results show that the model may be useful for estimation of thermal resistance in FinFETs and NWFETs with large layouts.

Modeling of Effective Thermal Resistance in Sub-14-nm Stacked Nanowire and FinFETs

Device self-heating effects (SHEs) in nonplanar Si MOS transistors such as fin field-effect transistors (FinFETs) and nanowire FETs have become a serious issue in designing well-tempered CMOS devices for future logic nodes. The device thermal contact resistances are strongly influenced by both the ambient temperature and within device lattice temperature. The ambient heat energy coupling through the thermal contact resistances will strongly impact device SHE in FinFETs due to increase in the surface-to-volume ratio of confined geometry thin Si Fin. In this paper, we report a 3-D quantum-corrected electrothermal numerical device analysis involving a coupled hydrodynamic and thermodynamic transport models for a target Si 3-Fin bulk n-FinFET. The numerical device simulations quantitatively predicted the impact of ambient and electrical contact temperatures on device short-channel effect immunity and performance. The simulation parameters are calibrated with the state-of-the-art Si FinFET measurement data from the literature. Our numerical simulation findings establish the phenomena of ambient temperature-induced device SHE on Si n-FinFETs performance for sub-14-nm technology nodes. The simulation predictions establish the fact that the thermal contact resistances and the within-chip ambient temperature ( ${T}_{A}$ ) have adverse effects on device lumped thermal resistance ( ${R}_{\text {th,eff}}$ ) and performance metrics. Finally, we have numerically analyzed the FinFET design solutions (tapered source and drain regions) to improve the tolerance against the ambient temperature-induced SHE.

Ambient Temperature-Induced Device Self-Heating Effects on Multi-Fin Si n-FinFET Performance

In this paper, the self-heating effect (SHE) in 14-nm bulk and SOI FinFETs are investigated through the TCAD simulation. To achieve high authoritative evidences, the calibration is performed by ${I} _{\mathrm{ D}}$ - ${V} _{\mathrm{ G}}$ curve fitting based on the experimental data. The main contributions include: 1) The distribution of heat generation and temperature gradient along the channel are disclosed. Two peeks of heat generation are observed in source extension (SE) and drain extension (DE), respectively; 2) The dependence of maximum lattice temperature and thermal resistance on device geometry and parameters including fin width, fin height, length of SE and DE, the thickness of STI and BOX, doping concentration of extension, and gate voltage, are thoroughly analyzed; 3) The influence of SHEs on the electrical characteristic of FinFET under different ambient temperatures are also revealed. Moreover, the critical heat removal paths of bulk and SOI FinFETs are discussed. For the former, most of heat vertically diffuses to the substrate, and then to heat sink, whereas in SOI FinFET it firstly dissipates to source, drain, and gate, and then to heat sink. Finally, several optimization thumbs of SHEs are proposed.

Impact of Geometry, Doping, Temperature, and Boundary Conductivity on Thermal Characteristics of 14-nm Bulk and SOI FinFETs

Self-heating and thermal modeling in fin-shaped FETs (FinFETs) are studied in this brief using calibrated 3-D TCAD simulations. Using the second order ${R}_{\textrm {th}}{C}_{\textrm {th}}$ network extraction, we demonstrate for the first time a simple method for the modeling of thermal resistances and capacitances for BSIMCMG compact models using small-signal ac capacitance method. We show that the extraction of thermal time constants using the second-order ${R}_{\textrm {th}}{C}_{\textrm {th}}$ method is superior to the other techniques used in the literature. Using this technique, we extract the thermal time constants for FinFETs to be in the order of a few nano/pico seconds.

A Novel TCAD-Based Thermal Extraction Approach for Nanoscale FinFETs

Thermal performance characteristics of fin-shaped FETs (FinFETs) are studied and analyzed in this paper for sub-22-nm technologies using the well-calibrated TCAD simulations. In this paper, we show that bulk FinFETs have a relatively better thermal performance as compared with SOI FinFETs. In order to understand the isothermal characteristics of these devices because of thermal effects, we use pulse rise-time as well as ac conductance methods. We demonstrate that the ac conductance method fails to accurately capture thermal time constants for FinFETs, as self-heating and gate resistance regions are indistinguishable from each other. A pulse rise-time method gives isothermal characteristics of these devices. As verified from both these independent techniques, only at high frequencies (>1 GHz), FinFETs show a suppression of thermally induced degradation, which can be attributed to their higher surface-to-volume ratio. It is observed that bulk FinFETs will perform better than SOI FinFETs for small effective fin heights. However, as we show in this paper, increased body doping in bulk FinFETs will increase the self-heating effects. Channel length scaling in FinFETs, which shows a decrease in drain current degradation with heating, will be an important design parameter for sub-22-nm devices.

A Thermal-Aware Device Design Considerations for Nanoscale SOI and Bulk FinFETs

Due to its infinite OFF resistance, Nano-Electro-Mechanical Switches (NEMS) have been recently proposed to reduce leakage current during the standby mode in large-scale Digital ICs in nano regime area. However, detailed analysis of the conditions at which the NEMS devices will have impact is missing. In this brief, the technique of power gating is analyzed with a NEMS switch using detailed circuit level simulations to obtain the conditions under which one can obtain net energy savings as compared with FinFET-based power gating. Finally, applicability in the energy reduction on a futuristic system-on-chip for mobile platform made using 14 nm gate length FinFET device is evaluated.

Ulayil Sajesh Kumar

Papers

A Thermal-Aware Device Design Considerations for Nanoscale SOI and Bulk FinFETs

Considerations for Static Energy Reduction in Digital CMOS ICs Using NEMS Power Gating