Showing papers by "Ulrich Rückert published in 2007"

Partial Dynamic Reconfiguration in a Multi-FPGA Clustered Architecture Based on Linux

Abstract: Dynamically reconfigurable hardware allows for implementing systems that can be adapted at run-time according to the needs of the user. This paper presents an architecture that is composed of multiple FPGAs that are connected to an embedded processor. Thus, the architecture is referred to as a multi-FPGA clustered architecture (MFCA). All FPGAs can be partially and dynamically reconfigured to integrate user-defined IP-cores into the system at run-time. For the resource management and communication management we have implemented a Linux operating system on the embedded processor that can be used to control the reconfiguration of the FPGAs by means of simple function calls. Furthermore, the Linux OS completely hides the physical infrastructure of the MFCA from user applications, offering a consistent interface to utilize partial reconfiguration.

GigaNoC - A Hierarchical Network-on-Chip for Scalable Chip-Multiprocessors

Abstract: Due to the technological progress in the semiconductor industry, more and more components can be integrated on a single die forming a complex System-on-Chip. For enabling an efficient interaction between the various building blocks of today's SoCs, efficient communication structures become more and more essential. In this paper, we present the GigaNoC, a hierarchical Network-on-Chip that is especially suitable for scalable Chip-Multiprocessor architectures. The GigaNoC approach features a packet-switched wormhole routing on-chip network that provides the backbone of our multiprocessor architecture. In order to meet bandwidth requirements of different application domains, our Network-on-Chip is easily scalable and parameterizable in various aspects. This work highlights the communication protocol and shows a performance evaluation for different congestion scenarios. Furthermore, we present an FPGA-based prototypical realization and introduce a debugging and verification environment. Finally, implementation results for a standard cell technology are discussed.

Stereoscopic Camera for Autonomous Mini-Robots Applied in KheperaSot League

Abstract: This paper presents a stereoscopic vision system for the mini-robot Khepera The vision system performs objects detection by using the stereo disparity and stereo correspondence The stereoscopic vision system enhances robot’s visual perception ability by grabbing stereo images and analysis 3D objects, while the robot doesn’t need to move The simple principle of our stereo vision is the less displacement of correspondence pixels shows that the pixels object is far away To realize the stereo vision and its calculation algorithms, the mini robot needs a powerful FPGA and micro-controller module as well as 2D color cameras An application of Khepera equipped with the stereoscopic camera is robot soccer in the KheperaSot league In the match, the robot has to be able to detect its environment, ie the ball, walls, goals and its opponent

Compiler-driven reconfiguration of multiprocessors

Abstract: Multiprocessors enable parallel execution of a single large application to achieve a performance improvement. An application is split at instruction, data or task level (based on the granularity), such that the overhead of partitioning is minimal. Parallelization for multiprocessors is mostly restricted to a fixed granularity. Reconfiguration enables architectural variations to allow multiple granularities of operation within a multiprocessor. This adaptability optimizes resource utilization over a fixed organization. Here, a unified hardware-software approach to design a reconfigurable multiprocessor system called QuadroCore is presented. In our holistic methodology, compiler-driven reconfiguration selects from a fixed set of modes. Each mode relies on matching program analysis to exploit the architecture efficiently. For instance, a multiprocessor may adapt to different parallelization paradigms. The compiler can determine the best execution mode for each piece of code by analyzing the parallelism in a program. A fast, singlecycle, run-time reconfiguration between these predetermined modes is enabled by executing special instructions which switch coarse-grained components like instruction decoders, ALUs and register banks. Performance is evaluated in terms of execution cycles and achieved clock frequency. First results indicate suitability especially in audio and video processing applications.

Defragmentation Algorithms for Partially Reconfigurable Hardware

Abstract: Dynamic reconfiguration is a promising approach for resource efficient utilization of microelectronic systems. Standard platforms for partial dynamic reconfiguration are field-programmable gate arrays (FPGAs). Multiple hardware tasks can share the same FPGA resources over time, which increases the device utilization in comparison to non-reconfigurable systems. Although, similar resource management is already known in the area of operating systems, there is a requirement to adapt these concepts to the special needs of dynamically reconfigurable systems. Additionally, there is a lack of underlying mechanisms, e.g., to suspend hardware tasks and restart them at a different position within the FPGA. In this article we introduce a mechanism for task relocation that includes saving and restoring of state information of the task. Based on this approach we address the problem of defragmentation. We present defragmentation algorithms that minimize different types of costs. With the help of a detailed simulation model and a benchmark, we finally provide realistic simulation results and compare the different algorithms.

Environment Exploration Using Mini-Robot Khepera

Abstract: This paper presents some results in the implementation of a local navigation strategy for environment exploration using real robot. As an experiment platform we used mini-robot Khepera II running in the Teleworkbench. The complete environment is divided into small quadratic patches with some objects placed in it. With on-board infrared sensors and wheel encoder, the robot can successfully explore the unknown environment. Moreover, by calculating the distance of surrounding patches, the implemented algorithm will minimize the distance traveled, in turn less energy and time. This paper also shows the advantage of using the Teleworkbench for performing experiments using real robots.

A multiprocessor cache for massively parallel soc architectures

Abstract: In this paper, we present an advanced multiprocessor cache architecture for chip multiprocessors (CMPs) It is designed for the scalable GigaNetIC CMP, which is based on massively parallel on-chip computing clusters Our write-through multiprocessor cache is configurable in respect to the most relevant design options It is supposed to be used in universal co-processors as well as in network processing units For an early verification of the software and an early exploration of various hardware configurations, we have developed a SystemC-based simulation model for the complete chip multiprocessor For detailed hardware-software co-verification, we use our FPGA-based rapid prototyping system RAPTOR2000 to emulate our architecture with near-ASIC performance Finally, we demonstrate the performance gains for different application scenarios enabled by the usage of our multiprocessor cache

A Digital Framework for Pulse Coded Neural Network Hardware with Bit-Serial Operation

Abstract: This publication presents a digital framework for building up pulse coded neural networks with leaky integrate-and-fire neurons and static synapses as well as dynamic synapses. The system, including a novel communication infrastructure, is mainly focused on ASIC synthesis but also shows a small footprint on Virtex2(Pro) FPGAs. Its bit-serial operation has been verified by simulations.

Real-Time Multiprocessor SoC for Mobile Ad Hoc Networks

Abstract: This paper introduces our Real-time Multiprocessor SoC intended for low power wireless application as mobile ad hoc networks. The multiprocessor is based on eight of our 32bit S-CORE RISC processors.

A Bluetooth Scatternet for the Khepera Robot

Abstract: Summary. Radio-based communication plays a vital role in multi-robot systems. Bluetooth is an energy-ecient communication technology suited for resourcelimited mini-robots such as the Khepera. However, the maximum number of nodes in a Bluetooth piconet is limited, while scatternets - networks of piconets - have not been fully specified. In this paper we present a Bluetooth scatternet using Bluetooth communication sticks developed in our research group. In our solution, bridge nodes carrying two of such Bluetooth sticks are used to interconnect piconets. Beside the developed hardware, issues such as routing as well as topology control are addressed. Finally, data rate and latency measurements are presented for the implemented solution.

Neural inspired architectures for nanoelectronics

Abstract: Extremely down-scaled field effect transistor, innovative manufacturing of semiconductors, novel material and computing devices have led to rapid changes in the semiconductor industry which now allows more complex systems and more computing power per chip area than several years ago Albeit these significant improvements novel technology nodes also offer unsolved problems to researchers and challenges to the designers In this paper, we give a brief overview about actual trends and problems in the semiconductor industry and how the upcoming tasks can be solved by the designers and researchers

Controlling complexity of RBF networks by similarity

Abstract: Using radial basis function networks for function approxima- tion tasks suffers from unavailable knowledge about an adequate network size. In this work, a measuring technique is proposed which can control the model complexity and is based on the correlation coefficient between two basis functions. Simulation results show good performance and, therefore, this technique can be integrated in the RBF training procedure.

Teleworkbench: A Remotely-Accessible Robotic Laboratory for Education.

Abstract: This paper presents a teleoperated robotic-laboratory named Teleworkbench and its benefit for educational purpose. It also presents briefly three issues that we need to take into consideration to make such a laboratory more effective.

Interference Suppression Technique for Diversity Selection Combining in an Indoor Environment

Abstract: In this paper a new diversity selection combining scheme called SSB (simplified switched beam) is given, as well as its test-bed implementation. SSB has apparent advantage in terms of size, power and complexity since it only requires one RF front-end and very few additional components. Furthermore, an interference suppression technique is designed, which can effectively mitigate the disturbance on correct diversity selection caused by interference. The intensive measurements made in an indoor environment show that this test-bed can closely approach the theoretical prediction on SNR gain and AF (amount of fading) made in [4] and [9] previously.

IAF neuron implementation for mixed-signal PCNN hardware

Abstract: In this paper, the implementation results of an integrate and fire neuron implemented in a 130 nm process are presented. This publication covers the properties of IAF neurons from calculations on an ideal electrical circuit modeling the soma of an IAF neuron and compares the theoretical results with simulation results from an extracted layout of the implemented neuron.

Impact of shrinking technologies on the activation function of neurons

Abstract: Artificial neural networks are able to solve a great variety of different applications, e.g. classification or approximation tasks. To utilize their advantages in technical systems various hardware realizations do exist. In this work, the impact of shrinking device sizes on the activation function of neurons is investigated with respect to area demands, power consumption and the maximum resolution in their information processing. Furthermore, analog and digital implementations are compared in emerging silicon technologies beyond 100 nm feature size.

A control approach to a biophysical neuron model

Abstract: In this paper we present a neuron model based on the description of biophysical mechanisms combined with a regulatory mechanism from control theory. The aim of this work is to provide a neuron model that is capable of describing the main features of biological neurons such as maintaining an equilibrium potential using the NaK-ATPase and the generation of action potentials as well as to provide an estimation of the energy consumption of a single cell in a) quiescent mode (or equilibrium state) and b) firing state, when excited by other neurons. The same mechanism has also been used to model the synaptic excitation used in the simulated system.

SSB: A new diversity selection combining scheme and its test-bed implementation

Abstract: SSB (Simplified Switched Beam) was originally motivated by a simple beamforming technique. It is expected to increase the performance of Mobile Ad Hoc Networks (MANETs) by associating with the dedicated MAC protocol [12]. However, we further find that it is a variation of the antenna diversity scheme, which is called GSC in [6] and H-S/MRC in [11]. SSB only requires one RF front-end and a simple additional processing unit, hence it has apparent advantage in terms of size, power, expense and complexity. Its 2.4 GHz test-bed for reception has been implemented recently. Intensive measurements show that SSB can help to suppress the effect of fading, enhance the SNR and finally result in the reduced BER.